ZX81 ULA Discussion

[Andy Rea]

I wonder why nobody ever built lots of Bodo's design when MACH210's were popular ?

[Paul]

I wonder why nobody ever built lots of Bodo's design when MACH210's were popular ?

That's a story that finally ended last march. Boards were designed and ordered. They were prepaid and got lost. Then discussions went over many years until finally Kai ordered new boards that were sold this year in march. Maybe there are still Kits available?
The project is still called ZX2000. It has an LCD driver onboard.
Saturday I made some more test with it. With a 10mhz CPU and a 24mhz quartz it was stable and fully functional running permanently on 12mhz CPU clock. The screen is also created much too fast but the LCD doesn't care and shows a brilliant picture.
I had test with 14 and 16mhz which both showed pictures hardly readable. Maybe the LCD is a bit selective. I didn't expect it to start up at 24 MHz but it showed to be ideal.
The only faster quartz I had in my box was a 40 (edited, 48 was wrong) MHz which did not run the ZX2000.

[PokeMon]

I think modern LCD's can be run with 32kHz horizontal / 100Hz vertical scan rates.
That's why I hope to get a useful picture with double frequency (13 MHz instead of 6.5).

[Andy Rea]

@Paul, no not the ZX2000, although i would like to play with LCD panels

Bodo did a plug in ULA based around the MACH210 CPLD....
this one. http://members.fortunecity.com/bodo4all/zx/zx81vid.html

i have seen it on a spanish (i think it was spanish) website but that also was only for personal use i believe.

Andy

[Paul]

The ZX2000 is the project that resulted from Bodo's FPGA design.
I Know you mean the high building part that was three times the height of a ZX81.
It's the next step. As the original design was too big they discussed on how this could be added to a board that fits in a ZX81 case. And easiest way to do it was to replace the whole PCB. LCD was added and there are many other enhancements so nobody thought about shrinking the whole thing until you did.

[Andy Rea]

Ah i get it now, it's an like an evolutionary thing

The first ever ULA replacment that i did out of some 23 ttl logic chips was never really meant as a serious thing, more a just because i can... and it was left at that for about 4 years, then i got hold of some GALs quite cheap, knowing in advance that my eprom programmer could program them , that was quite a leap for me, so the 23 ttl chips were replaced with 6 Gals and 1 TTL a 66% reduction in real estate...

Then some bright spark (wonder who that might be) wondered if it could be done in CPLD like BODO's design, i took a look at his source and frankly at that time could not work out one thing fom another it was like gobbled gook to me. So the question was should i accept the challenge, and of course me been me how could i refuse.

i downloaded the altera software and started to play, at first i couldn't even get a simple 'and' gate to work, so a small step back and i had a quick look at the available hardware description languages, and plumped for verilog as been reasonably easy to learn and be able to read back previous code and work out whats going on.

Many idea's come and go, many hours of head scratching, and many watery eyes starring at scope traces and logic traces but finally i believe i have the correct ULA behaviour, and i'm sure it has been said before as long as what goes in and out of that 'black box' is the same as an original it matters not what acutally happens inside the box.

My i waffle sometimes....

Regards Andy


P.s Rich is it possible to move the latter part of this thread to a more suitable board, it seems to have drifted away from been a sales advert

[zx80nut]

Hi.
Yeah, I've been looking (glazed over a bit) at bodo's sourcecode.
I'm currently trying to get to grips with a bit of VHDL after installing the ridiculously huge Xilinx ISE Webtool suite.

I'll probably go for a 3.3V (5V I/O tolerant) CPLD, as they are so much cheaper than the 5V versions, so I can buy a few.

Currently I don't know what size chip to get, though, as I don't know how many macrocells are needed. Retrotechie seemed to need more than Bodo, as I the Mach 210 only has 64.

The XC9572 has 72 macrocells (yeah, obvious from the name ) so I assume that should be OK. I only want the "standard" ULA functions.

Andy, Retrotechie, are you guys going to be publishing your sourcecode sometime ? I don't want to copy (it's the challenge that makes it worthwhile, as you have found out ) but I may need pointers when I get stuck.

Grant

[Andy Rea]

Hi Grant,

Nice to see your having a go the development software is rather large, i reckon a basic ULA can be done in around 44 macrocells, my 2 chip version used 37 but of course you would need 6 more for the char-code latch (which was done in a gal) on that version, the MK2 uses 84 (out of 128) but of course that has much more to do, 8 are used for a 1 byte memory, and a very wasteful 12 in the clock-gen module but done very much on purpose and only works on this device, a faster/slower device would yeild different result, but it allows a poor 6.5Mz (i.e 20% thru to 80% duty cycle input clock) and gives 6.5Mhz at about 45% duty cycle (close as i could get it) and of course the 3.25, also the edges (rising edge of 6.5, both edges of 3.25) are in sync, the 6.5Mhz is if you like double buffered so the final output gets 'clocked' on the same edge as the 3.25Mhz output. right you understood all of that didn;t you

Well i might publish the code eventually, I need to copy the entire project so i have the working original 'safe' and then set about annotating and giving things names that make sense. I would like to do a kind of write-up on how the whole thing has evovled over time. might make an interesting read, but for me that is a big ask, i'm not really one for documenting things. i'm more of a get stuck in person.

yeah 3.3v chips will work, and they are loads cheaper.

Regards Andy

[Andy Rea]

i think you need 38 io's but can do away with 2 if a) you always assume 50Hz no uk/us pin connection b) no tape input. and if your going to use jtag to program with altera you can't use the jtag pins... more io's you can live with but just 1 not enough is disaster...

EDIT mach210 has 32 io's and 6 dedicated inputs, total 38.

Andy

[zx80nut]

Thanks for the info, Andy.

I'll put a Farnell order in shortly

Regards.

Grant