Discussions about Sinclair ZX80 and ZX81 Hardware
mikeh_nz
Posts: 67 Joined: Sat Feb 04, 2023 8:03 am
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by mikeh_nz » Wed Apr 26, 2023 6:20 am
1024MAK wrote: ↑ Fri Nov 04, 2016 9:52 am
/RAMCS goes to both pin 20 and pin 22 of the RAM socket.
Mark
Hmm - that could the be the reason, I’m only feeding into pin 22 and letting the regular “clipped” signal still feed into pin 20.
I’ll try putting the computed /cs into both pins 20 & 22
mikeh_nz
Posts: 67 Joined: Sat Feb 04, 2023 8:03 am
Location: Seattle
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by mikeh_nz » Wed Apr 26, 2023 8:03 am
And that was the problem.
Interestingly - it works perfectly (no artifacts) when I compute /cs and feed it into pins 20 & 22.
But the OR gate (or 2 OR, or 3 OR gates in series) between the board’s /cs signal and pins 20&22 doesn’t work at all - same artifacts.
At the moment I’m using a 74LS00 (quad 2-input Nand) & a 74LS32 (quad 2-input OR) to compute /cs (picture below).
Any suggestions on how to do this more efficiently? (say just one chip).
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Current way I’m computing /CS
Last edited by
mikeh_nz on Thu Apr 27, 2023 5:47 am, edited 3 times in total.
1024MAK
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by 1024MAK » Wed Apr 26, 2023 2:25 pm
Yes, both the SRAM /CS and /OE inputs (pins) need to be controlled. As the SRAM will only drive the data bus when both are active (logic low).
You only need two NAND gates in your circuit. So half a 74LS00 will do.
Mark
mikeh_nz
Posts: 67 Joined: Sat Feb 04, 2023 8:03 am
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by mikeh_nz » Thu Apr 27, 2023 3:50 am
Thanks Mark,
What would it look like with just two NAND gates? I think I need 3 (one to mimic a NOT, and two to mimic an AND)
Question: I initially tried without the “no-op OR” (ie after the A14 NAND) but it didn’t instantly work and it felt like for timing purposes, I had to have the same number of gates before the final OR - does that sound right? (ie these gates take time to execute I assume)
From searching the web, I think I can do all of this logic on a single 7450 TTL chip - I’m going to purchase one on eBay and have a go.
Below is a picture of the plan… it might actually have enough space to sit nicely on top of the ram chip like a Spectrum spider (and hopefully not like a Spectrum dead cockroach)
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1024MAK
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by 1024MAK » Thu Apr 27, 2023 9:30 am
/MREQ and /RFSH into the first NAND. The output of this and A14 into the second NAND. Output to the SRAM /CS and /OE pins.
However, although the logic should be correct, I’ve not tried this with a fast SRAM chip.
Mark
mikeh_nz
Posts: 67 Joined: Sat Feb 04, 2023 8:03 am
Location: Seattle
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by mikeh_nz » Sat Apr 29, 2023 1:04 am
Doh! Why didn’t I see that logic equivalency!
So I tried this out with the SN74LS00 and it doesn’t work - I think there are speed issues.
But trying with a SN74HC00 does work for me. Nice!
mikeh_nz
Posts: 67 Joined: Sat Feb 04, 2023 8:03 am
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by mikeh_nz » Sun Apr 30, 2023 7:51 pm
I've also tried the SN7450 idea above - it did not work (I assume more timing issues).
So it seems that the result is:
Use a capacitor if you can. Simplest approach. (Ive seen 33pF to 100pF work depending on the board Ive tried it on)
If a capacitor doesnt work for you, try a 74HC00 logic gate - it can quite nicely piggy back on top of the RAM chip.
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Nice spot for the capacitor
74HC00 logic chip
mikeh_nz
Posts: 67 Joined: Sat Feb 04, 2023 8:03 am
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by mikeh_nz » Fri May 05, 2023 3:55 am
Here’s the 74HC00 mounted on top. It’s more of an “octopus” than a “spider” but it works…
Edit: updated photo given the feedback below…
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Last edited by
mikeh_nz on Sat May 06, 2023 6:41 am, edited 2 times in total.
1024MAK
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by 1024MAK » Fri May 05, 2023 3:25 pm
Neat work
Just a small point. But with CMOS type chips like 74HCxxx or 74HCTxxx, all unused inputs (even for unused gates) should be connected to either the supply (+5V) or 0V/GND to prevent undesirable effects due to the inputs picking up stray voltages.
Mark
mikeh_nz
Posts: 67 Joined: Sat Feb 04, 2023 8:03 am
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by mikeh_nz » Sat May 06, 2023 3:20 am
Thanks Mark,
I’ve updated the photo above to reflect this…