ZX81 ULA-in-a-CPLD

[RetroTechie]

Why didn't I try this before...
Let's hope the file size isn't an issue for maintainer(s?) of this site - it shouldn't be I think, as this is low-traffic material.

ZX81_ULA-in-a-CPLD_v1.10.zip

Full project description & sources (schematics)

(1.78 MiB) Downloaded 2588 times

I wonder what the utilisation of the CPLD is like? I'd be tempted to see if I can put the design in an Altera CPLD since I've been playing with those lately.

My design uses 59 macrocells from a 72 macrocell CPLD (Xilinx XC9572). So with a bit of luck it might fit in a 64 macrocell Altera CPLD. But that would be a tight fit. Unfortunately 128 macrocell Altera devices I know off, come in 100 pin QFP packages. Which is just a little too big to fit onto a 40p-DIP footprint (although Andy somehow managed that anyway ).

ZX81 ULA logic isn't very complex - a few counters, a few flipflops, an 8 bit shift register, and some logic tying things together. Understanding how everything works together in a ZX81 is the hard part IMHO. A 64 macrocell will probably do if all you need is a 'vanilla' ZX81 ULA replacement. If you want to add extra's like clock doubling/tripling, a blockswitching mechanism for the RAM etc, then better go for a 128 macrocell device.

You'll also need 5V tolerant inputs, and personally I have a strong preference for not starting new designs using parts that are considered obsolete. So for this application I'd be looking at Xilinx 9500XL (XC9572XL in VQ64 package would be a nice choice), or Altera MAX 3000A family.

[zx81user]

Thanks again for the detailed description! Yes, if people want to try this themselves, I suggest to do a good study of the ZX80 schematic first. Then, understanding the CPLD circuit as drawn by RetroTechie, although slightly different, is easy to follow. Now, I would like to see the same circuit but programmed in VHDL or Verilog just for comparison/study.

A very nice ZX80 schematic is this one:
http://nocash.emubase.de/zx80-sch.gif

Detailed descriptions can be found here:
http://searle.hostei.com/grant/zx80/zx8 ... 0Operation

Michel

[Paul]

Again I need to push you into Andys Direction.
He will give you his design which is in either vhdl or verilog, I do not remember.
Holmatic on the other hand has made his ULA in the other format. If you get his design as well he (as I have) you will have all three design methods (I know of) on your computer.
Holmatic's ULA is also Altera based. He uses it for his hybrid machine that also has Jupiter ace inside. His blocks are clearly separated into the machines so no problem.
Sorry that I can only give primitive hints. I am still a beginner to cpld's.
kind regards
Paul.

[Rink]

Again I need to push you into Andys Direction.
He will give you his design which is in either vhdl or verilog, I do not remember.

Cheers Paul. I don't want to bother Andy yet while I'm just thinking about things. I've no use for a ULA replacement at the minute; it's more an interest born of curiosity or a learning exercise.

You'll also need 5V tolerant inputs, and personally I have a strong preference for not starting new designs using parts that are considered obsolete. So for this application I'd be looking at Xilinx 9500XL (XC9572XL in VQ64 package would be a nice choice), or Altera MAX 3000A family.

I LOVE the MAX3000As. I'm pretty close to putting one in every project just because I enjoy playing with them so much.

Taking a look at your file now, cheers mate.

[commie]

Hi Chaps,

I've implemented the zx81 ula in an Atmel ATF1504 (plcc44) cpld and its working great except for one feature, that is it doesn't work in slow mode only fast mode with the nmi pin strapped high. When I connect the nmi I get garbage on the screen, but the nmi pulses are active as seen on my scope. I have checked everything over and over again but I cannot see any mistakes.

As is in fast mode, everything works perfectly and the picture is super stable, powers up perfectly first time.

If you are wondering how I sqeezed it all in plcc44, well the oscillator and flip flop(3.25MHz) are external and drive only the z80 whilst 6.5MHz osc. is fed into the cpld where the 3.25MHz and /3.25MHz are derived in the cpld.

I realise it's a difficult problem for anyone with just the above info. but I am so close to having it work in slow mode aswell.

Cheers
commie

[sirmorris]

CPLDs can be very tricksy sometimes. A slight re-arrangement of logic or change of a configuration bit can be the difference between working and not

[commie]

I might just add that I'm using retrotechie's Xilinix implementation and ported it over to the Atmel atf1504 plcc44. Well, I'm at a loss as to why it wont work in slow mode? Everything else including the tape load/save works perfectly, but only in fast mode.

cheers
commie

[PokeMon]

CPLDs can be very tricksy sometimes. A slight re-arrangement of logic or change of a configuration bit can be the difference between working and not

Indeed, can be undetected race conditions occur depending on the compiler and declaration but there are sometimes hardware problems as well. CPLDs are very fast and sensitive for smallest spikes due to high input impedance. Sometimes I do a correction while adding a capacitor at some input or a series resistor to slower fast signals or eliminate spikes.

[commie]

Can I just make it clear, everything works perfectly, the picture is rock steady there are no glitches or hic ups on the screen, all the scope waveform's look good no glitches. In fact, it's working so good I am contemplating building it on a pcb and using it as a basic language platform as is.

However, does anyone know what the differences are between fast and slow modes?, I know that the nmi is used in slow mode, what changes take place in the zx81's hardware/software?.
It is so tantalising close to 100% working, I've simply got to find out why it wont work in slow mode.

[PokeMon]

Glitches can occur under specific circumstances and may not be seen on screen but regularly end in system crash. Just a flipflop taking a spike from a neighbor track because CPLDs are extremely fast and may react on spikes <5-10ns. Just to keep in mind - not sure if there is a general problem. Could be that redefinition of clock lines in the CPLD could have some effect and could be that this occurs during slow mode only.

The only difference is that the NMI is switched on and off during slow mode. Maybe the sync nmi section is the problem with the WAIT line as well. This is used to halt the CPU and let it run further on a defined clock cycle.