How does Wilf's shadow ROM block swapping work?

[hackdog]

Several of Wilf Rigter's designs use an improved memory decoder based on a 74HC251 multiplexer: Thanks for all the memories, ZX RAM I/O, ZX97 Lite. I'm puzzled by the switch that allegedly swaps the 8K block in the address space of 0-8K in ROM with the block in 32-40K in RAM.

If I understand it correctly, the multiplexing works as follows. The top three address lines are tied to the three binary inputs, representing a binary number from 0 to 7. This partitions the entire 64K address space into eight blocks of 8K each. The multiplexer also has eight linear selection inputs; each one therefore corresponds to an 8K block.

When a particular 8K block is being addressed, output Y is set to the logic level of its corresponding linear selection input; output W is simply set to the inverse value. Y and W then drive /RAMCS and /ROMCS, activating either the RAM or ROM chip for the address on the bus. So by assigning a low or high logic level to a given linear input, we can choose whether an address in that block will be picked up by the RAM or ROM. That's straightforward enough.

However, in order to swap blocks in the memory space, i.e. remap them, you'd have to adjust the address lines themselves. And according to the datasheet, the address lines are strictly inputs.

Perhaps only the roles of RAM and ROM are being swapped for these blocks: i.e. 0-8K ROM is swapped with 0-8K RAM and 32-40K RAM is swapped with 32-40K ROM. But that wouldn't be very practical, as you wouldn't be able to write into the 0-8K RAM space before the swap because the ROM is in the way. And it also doesn't fit the descriptions given in Wilf's and Rodney Knaap's ZX97L articles.

So, what's going on here?

[1024MAK]

Let’s take an example from Thanks for all the memories.

Let’s start with A13, A14, A15 all low.

So 74HC251 inputs A, B, C all low. That means that output Y will be the same logic level as input D0. This comes from U2c and in turn simply depends on the position of the shadow ROM enable switch. However, both outputs (Y and W) will only be active IF the /G input (pin 7) is low. This input pin is controlled by various NOR and NAND gates that perform memory map decoding, take the output of IC U2c and the state of the Z80 /RD line and hence it is this block of circuitry that determines if the Z80 will see the machines ROM, or see a read only area of one of the RAM chips or allow read/write access to RAM. If RAM is selected IN the ‘ROM’ area, this circuit also drives the /ROMCS line high to disable the machines internal ROM chip.

Note that when /G is high, both Y AND W outputs will go to the high impedance (hi-z) mode. Then the two 2kΩ resistors pull up the /RAMCS lines to the two SRAM chips, thus disabling both of them.

If you draw up some truth tables, you can then work your way through each state of A13, A14, A15, /RD and see how the circuit works for each 8K byte memory block

Mark

[hackdog]

Thanks! I'll need more study because I haven't seen the light yet. I can sort of understand how the Z80's control signals (/RD, /RFSH, /MREQ) are being decoded because of the peculiar video subsystem. In "Thanks for all the memories" A13, A14 and A5 are connected both to A, B and C and U2a and U2b for decoding. The ZX97L memory decoder is similar but simpler, just having A13, A14 and A5 connected to A, B and C, so I think I'll concentrate on that one first.