Okay, some news good and bad for you.
The bad one is, there will be a small delay in delivering as I got an idea to improve the system. The good is, you get a better ZXmore.
I need a new/bigger CPLD for that and change the already programmed EPM3032 against EPM3064 with 64 macrocells instead of 32.
The 32 are now used to 100%.
Yesterday I took a look in the sources of the ZX Spectrum ROM and found out, that the AF' register is not reserved for use in the NMI routine but used several times in the code, mainly during SAVE and LOAD but for other purposes as well. This conflicts with the usage now as margin line counter. I could fix this behaviour by patching some rom locations and replace EX AF,AF' instructions with corresponding PUSH AF / POP AF combinations but I fear that this instruction may be used in user programs/applications as well.
Thinking further there might be CP/M applications as well using the AF' register. My display routines don't use IX and IY register anymore but still use AF' register for the 55 or 31 margin lines depending on PAL/NTSC mode. So to get rid of this register I could use a variable in memory as well but it would take much more time in the NMI routine to switch the latches to instance 0 and back which would slow down the speed of the ZXmore. I now have the idea to replace the 55 NMI's plus 1 sync NMI with just 2 NMI's and have a long period of 55*64us=3.5ms with uninterrupted time for application and one fast NMI with 64us for synching the display. This would in the end fasten up the whole machine as I don't need to decrease a counter at all and let this job do the CPLD.
Luckily all signals needed are present and I just need about 16 additional macrocells to setup a 6 bit binary and partly programmable counter and a changed NMI handling - that's it. This won't need any changes in the already fixed firmware 0.9 and is a hidden feature activated with the next release. I just need the other chips and play around a few hours to test this feature which is not activated by default (or set to one hsync per NMI).
I think this feature is worth to wait a few days more and just ask for your patience.
The other option would be to do a hardware update with the next release but I don't like that and would be much more complicate.
I think this would be the last programmed option.
I like the CPLD quite much and it saved my bacon with easy change of business logic when desired later. I am still not convinced that it is a good idea to do all in a CPLD as there are only 34 signals available but can put quite much logic inside. Luckily the 64 macrocell CPLD has the same case and pinout.
