DRAM control circuits
Posted: Sat Jun 02, 2012 5:20 pm
In this thread I offered to provide some details on how some of the other non-Sinclair designs of RAM packs use standard 74LS TTL chips to interface DRAM chips.
As Aurel (makeit2day) has asked for this info, here it is in the attached zip file.
Included are one version of the Memotech 16k RAM pack circuit, the PANDA 16k-byte RAM pack circuit, a circuit from an unknown make (because when I got it, it was uncased) and finally the circuit that Memotech use in their MTX computer.
In all cases each data line (D0 to D7) goes to the data line (input and output) connections on each DRAM chip. Address lines A0 to A13 (for ZX81) go to two 74LS157 "two to one line selector" chips. The outputs from the 74LS157's go to all the DRAM chips. Note that the Z80 address lines A0 to A6 have the address for refresh on them, so these must be the lines selected by the 74LS157's and routed to the DRAM chips when /RAS goes active to logic low, so that the DRAM chips can refresh correctly. Other than that, the order of the address line connections is non critical.
As far as I know the details provided are correct, but as all the ZX81 RAM pack details have been reverse engineered, if you find an error or something does not make sense, please let me know
Mark
As Aurel (makeit2day) has asked for this info, here it is in the attached zip file.
Included are one version of the Memotech 16k RAM pack circuit, the PANDA 16k-byte RAM pack circuit, a circuit from an unknown make (because when I got it, it was uncased) and finally the circuit that Memotech use in their MTX computer.
In all cases each data line (D0 to D7) goes to the data line (input and output) connections on each DRAM chip. Address lines A0 to A13 (for ZX81) go to two 74LS157 "two to one line selector" chips. The outputs from the 74LS157's go to all the DRAM chips. Note that the Z80 address lines A0 to A6 have the address for refresh on them, so these must be the lines selected by the 74LS157's and routed to the DRAM chips when /RAS goes active to logic low, so that the DRAM chips can refresh correctly. Other than that, the order of the address line connections is non critical.
As far as I know the details provided are correct, but as all the ZX81 RAM pack details have been reverse engineered, if you find an error or something does not make sense, please let me know
Mark
Got a schematic of that machine somewhere?
Basically: /MREQ low -> /RAS low -> short delay -> flip address multiplexers -> short delay -> /CAS low. Those delays sometimes implemented using Z80 clock, sometimes with simple RC delays (both methods have pro's and cons). And many variations on that theme (with /CAS-before-/RAS refresh being one).