OOMFIE (Memory board)

[Mustermann]

Things the world doesn't need, but that were a lot of fun to build:

OOMFIE Only One Memory For Internal Expansion

It is what the name say: An internal memory expansion (for ZX81, issue 3 boards only)

I'd like to build my own internal UDG capable memory expansion. This is the result.

Some features:

96k of RAM
0-8k ROM overlay, switchable for character set or code or both
8-32k RAM
32-64k two banks of RAM (switchable)
All battery backuped

HRG:
Pseudo HRG work
WRX work
UDG work
CHR$128 work

Connection
All pin contacts
No cables

Made to fit inside of a standard ZX81 housing

Can be disabled by any external expansion

Details, schematic and Gerber files available.

[Mustermann]

Schematics part 1: Main address decoder

This part replaces /ROMCS and /RAMCS
Forcing /ROMCS or /RAMCS from the backside connector will still disable ROM or RAM.

JP5 and JP4 select one of this ROM overlay modes:
open, open: ROM active in read and refresh cycle. Date written to RAM in write cycle. Just to populate overlay RAM.
close, open: RAM replace ROM in 0-8k, not writeable anymore but still read from ROM in refresh cycle
open, close: Code is still read from ROM, but characters are read from write protected RAM in refresh cycle. This requires J3 set as well.
close, close: Code and characters in 0-8k are from RAM. This area is write protected and require J3 set as well.

RAM in 8k-64k is accessible with /MREQ and /RFSH.
RAM /OE is only active if /RD or /RFSH is active.

ULA is no longer in charge for /ROMCS or /RAMCS

[Mustermann]

Schematics part 2: A15 Logic

This is a standard A15 logic.
A15 will be pulled to 0 if /M1 is 0 and A14 is 1.

In addition to that A16 is used for memory paging
If A15 is 1, jumper choose one of two banks.

So no paging in 0-32k and if /M1 is 0 also not in 48-64k.

Data can be written to and read from both banks in 48-64k. In /M1 cycle 16-32k is mirrored in all cases.

[Mustermann]

Schematics part 3: WRX / UDG logic

When using WRX hires scheme A0-A8 of RAM are provided by the CPU.
This is the standard for most internal and all external RAM packages.

If you want to use UDG scheme, you need to provide A0-A8 from ULA cycle in the the same way than ULA provide it to the ROM.

To make it both available you need a switch. This is done by 3x 74HCT157 that either forward A0-A8 from ULA or from CPU to the RAM.
The jumper chose which one is used.

Both signals are available at R18-R26. To make it easier to connect with the board I removed all of these resistors, connected both sides to the expansion and added the resistors to the expansion board.

This will work with 74HCT157 or 74HCT257.

[siggi]

Nice project.
Is it possible to write-protect the "0-8k rom overlay", if it contains e. g. patched rom code?

Siggi

Oops: I missed the description of the jumpers ...

[XavSnap]

Yep,

It's a nice project!

This machine has a future, and this kind of project ridicules the original machine.
Like it...

[Mustermann]

From my point of view it is much more stylish to have it all in one chip as the ULA is.
But knowledge and ability to create those things trend to fade away.

Ok, Sinclair ULAs are an exception, as content is well understood and replacements are available.

Nevertheless, I tend to use as common parts as possible to make it understandable and rebuild-able.

So the most unusual part is the DS1210. But this will be introduced in schematics part 5.

[Mustermann]

Schematics part 4: CHR$128

To enable 128 user defined graphic characters some additional logic is needed.
First standard UDG need to be activated.

Within M1 cycle the status of the inverse bit (D7) need to be latched.
In RFSH cycle the latched data will replace A9 to select one of 2 subsequent character sets.

So different characters can be used for standard and inverse characters.

The circuit is a bit strange as I did a bad mistake in version 2 of the board and had to fix it with the logic gates that were in place.

The lower part is easy: D7 is latched on the rising edge of M1. To avoid a race condition D7 is delayed by two inverters.

The three NAND on the top chose either latched D7 or A9 for output.

The two outputs of the second latch are able to chose one of the signals.

As long as /RFSH is 1 (all other cycles except of RFSH) A9 is selected.
Within RFSH cylce the falling edge of /MREQ is latching the value of the jumper and this chose either A9 (UDG) for the output or latched D7 (CHR$128).

There are a hundred other solutions to do this but not so many if you have 2 inverter and one latch left.

[Mustermann]

Schematics part 5: Battery backup

This is the silver plated solution for battery backup a SRAM.
The DS1210 was made for this purpose.

If Vcc is above defined level CE is forwarded to RAM and power is supplied from Vcc.
As the voltage falls below the level, CE is kept on H and the RAM is supplied either from Vcc or the battery.

If you wanna make it golden plated, a second battery can be added.

[Mustermann]

Enclosed are the Gerber files and the all in one schematics.

They are hereby released at your own risk for any non-commercial use.

I can only say that they have worked for me (once so far), but I take no liability that there are no errors in them or that my skills were not sufficient to fulfill any regulations.

Feel free to use it as a template, double check everything carefully and use it at your own risk.