ZX81 RAM pack Issue 3 (ULA 1H035E) DRAM refresh
Posted: Sat Jul 24, 2021 4:54 pm
I've been investigating the Ferranti ULA 1H035E used in the ZX81 RAM pack Issue 3. One aspect of this that is as yet a mystery to me is how the DRAM in this particular RAM pack is refreshed.
For the Issue 1, an analysis of the schematic that is widely floating around shows the following. I think. (Throughout all of this, both /RD and /WR, as well as /M1, remain inactive.)
Step #1
Step #3 (about 325ns later since 1 cycle)
Anyhoo, this is about DRAM refreshing on the Issue 3. This is a different beastie because of ULA IH035E instead of the OR gate, NAND gate, 1 of the multiplexors and the counter.
Here's the pinout of this chip:
Thinking about the address inputs on the 4116s:
One answer I know is wrong would be the hypothesis that the ULA has an internal 7-bit counter i.e. an equivalent of the 393 used in the Issue 1. This can't be the case because part of the row ID on the Issue 3 must be one of the outputs from its 157 i.e. either A10:A7 or A3:A0 from the address bus of the base system i.e. it would be picking up at least part if not all of the value of I:R. The bothersome thing about this is that I is a fixed value and R is reset to specific values for video generation.
Help! (Please )
For the Issue 1, an analysis of the schematic that is widely floating around shows the following. I think. (Throughout all of this, both /RD and /WR, as well as /M1, remain inactive.)
Step #1
- Z80 pulls /RFSH active during the first half of M1:T3
- As /RFSH goes active, the inverted signal is used to pulse the 393 row counter and select the multiplexed counter (instead of A7:A0) for the 7-bit row ID to refresh.
- As /MREQ goes inactive, the high address is selected.
- /RAS line is pulled inactive by /MREQ.
- During the second half of M1:T3, the Z80 pulls /MREQ active.
- As /MREQ goes active, the high/low multiplexor selects the low address, itself multplexed to the counter.
- /RAS line is pulled active by /MREQ.
Step #3 (about 325ns later since 1 cycle)
- During the second half of M1:T4, the Z80 pulls /MREQ inactive.
- As /MREQ goes inactive, the high/low multiplexor now selects the high address A13:A7 (which will have part of the value of I:R).
- /RAS line is pulled inactive by /MREQ.
- Starting the new T1, the Z80 pulls /RFSH inactive.
- As /RFSH goes inactive, the inverted signal is used to select the multiplexed counter back to A6:A0.
Anyhoo, this is about DRAM refreshing on the Issue 3. This is a different beastie because of ULA IH035E instead of the OR gate, NAND gate, 1 of the multiplexors and the counter.
Here's the pinout of this chip:
Code: Select all
A11 [ 1 U 20] Vcc
A12 [ 2 L 19] 4116:a4
A13 [ 3 A 18] 4116:a5
A4 [ 4 17] 4116:a6
A5 [ 5 I 16] 4116:/WRITE
A6 [ 6 H 15] 4116:/CAS
/RFSH [ 7 0 14] 157:SELECT
/MREQ [ 8 3 13] 4116:/RAS
A14 [ 9 5 12] /WR
Vss [10 E 11] /RD
- {a6,a5,a4} come from the ULA (which presumably has an internal multiplexor for {A13,A12,A11} and {A6,A5,A4}
- {a3,a2,a1,a0} come from the 74LS157 multiplexor where the ULA selects either 0:{A8,A7,A10,A9} or 1:{A1,A0,A3,A2}.
One answer I know is wrong would be the hypothesis that the ULA has an internal 7-bit counter i.e. an equivalent of the 393 used in the Issue 1. This can't be the case because part of the row ID on the Issue 3 must be one of the outputs from its 157 i.e. either A10:A7 or A3:A0 from the address bus of the base system i.e. it would be picking up at least part if not all of the value of I:R. The bothersome thing about this is that I is a fixed value and R is reset to specific values for video generation.
Help! (Please )