Sinclair ZX80 / ZX81 / Z88 Forums

Hi everyone!

I'm hardware-innocent and for the two days I've been looking into clock doubler designs that I could build cheaply and easily.

Unfortunately even the simplest and latest designs from Wilf date from 2003 and still needs 3 IC and enough ability to be able to build the circuit correctly.

The most interesting and simplest solution I actually found was a replacement ULA (from Randy?) with its own updated clock signal but it doesn't seem to be available anywhere.

So my question is, since microcontrollers like the Atmega328 now can run at 16 Mhz (faster than the 6.5 Mhz clock signal we want), would it be possible (and easy? ) to use one to replace all the IC logic with a few lines of code instead? And add new functionality as a bonus on top like, I don't know, bank switching?

If this is a dumb idea please feel free to educate me, I really am just starting out in hardware.

Feeding a ‘double rate’ clock to a Zeddy is not the difficult part.

The ULA is designed for a 6.5MHz clock, which it then divides by 2 to generate the 3.25MHz CPU clock.

To run at a higher speed, the existing Z80 microprocessor needs upgrading to a 8MHz or 10MHz part (or you could try overclocking a 6MHz part, but these are less common anyway).

The RAM and the ROM must also be capable of running at 6.5MHz (so you will need chips with a faster access time).

Then the next snag is that being as the internal counters in a ULA are designed for a 6.5MHz clock, the Z80 is intended to be run at 3.25MHz, and the ROM code is also designed for this speed, hence if the system is run at a ‘double rate’ clock, the video signal that is produced will just be an out of specification load of electrical noise to a TV. A TV will no longer recognise the signal as a valid video signal...

Andy Rea (of this forum) did at once stage design, build and supply his new ULA modules, he put a lot of work in and was able to include a ‘double rate’ system. IIRC when the system tried to display a TV picture, the system dropped back to normal speed. Alas, the parts he used are no longer available, hence this ULA module is also no longer available.

Mark

"Randy" = Andy Rea, doh, thanks for sorting me out, seems obvious in hindsight.

As for hardware requirements, as far as I can tell the ZXpand+ can handle 6.5 Mhz so RAM speed shouldn't be a problem?

The whole idea of the Baker/Rigter "clock doubler" is to drop down to "SLOW" 3.25 Mhz clock whenever there's a video interrupt. (http://www.user.dccnet.com/wrigter/inde ... /turbo.htm)

I am simply wondering if someone could "emulate" the circuit in a 6$ microcontroller quickly enough to keep everything in sync with only 9 wires to solder. After all fast microcontrollers weren't really around when that circuit was designed.

Thanks

For a microcontroller to respond in time, it must be able to execute all the instructions it needs to between the changes of state of the system you are connecting it to. So for example, if it sees an input from the Z80 change state, it may have to do a comparison, do a jump, process some data, load a value into a register, then output to its port pins. And all this has to happen before the next clock tick of the Z80s clock input to guarantee that the Z80 sees a steady state when it samples its inputs...
So the really, really fast microcontrollers may be useful for performing some of the logic functions, but a 16MHz microcontroller would not be fast enough.

Andy Rea used a CPLD which has programmable logic that is very fast. And being combination logic, each logic block works in parallel (unlike a core reading software instructions like a Z80 or a microcontroller).

Does that help (if that’s an appropriate use of the word ‘help’ )?

Mark

Okay, my idea was to assume that the required clock pulse would follow a predictable pattern, 3.25 Mhz when displaying a char, 6.5 Mhz otherwise, so you could literally write a program with a line for every pixel or scan jump to generate the clock pulse or skip it (for half speed). Run the MC at 6.5 Mhz and you're all set.

But after reading the "why wait" circuit I can see that the CPU's response to the NMI has an unpredictable latency, so I'm guessing the required "specific edge of the clock cycle" to load the displayed byte would go out of sync. I guess that shows why the X1 "crystal" isn't used to drive the whole machine but is instead slaved to the ULA...

I'm not sure I really grokked the whole thing yet, but thanks for humouring me.

My current project should be run in FAST mode so I'm not sure why I'm thinking about this anyway

The other problem with trying to predict a ZX81, is that different machine code programs that use their own display driver code, may have different timings.

Mark

Don’t make the mistake to compare the speed of microcontrollers and logic/cpld.

Microcontrollers are like a smart man that can do many different things.

However logic/cpld is like a whole factory. The factory is not that versatile, many people work in there in parallel each person instantly available for their specific task.

I must persist I think I have a heat stroke, my brain isn't working very well so I just can't stop thinking about this.

The zx81 expansion port has basically all the signals a clock doubler needs, /IORQ, /HALT, WR and so on, and of course /CLK. Could a simple expansion be made to hold the logic (a few gates and flip-flops) and return the wanted frequency straight to the base of TR2 using an extra wire?

The (future imaginary ) ZXPand+2 is clpd so it could be fast enough to switch the clock signal correctly on a new optional clock wire right?

Also I know that would mean pulling a wire through the case more or less permanently for a meager speed gain in SLOW mode (30%?) but worth it in FAST mode if the damage to the case is light enough.


Post-scriptum:
At first I thought I could just shove the selected clock up pin 6B but that would just get halved anyway; shows you how much my brain needs a rest.
(edited some goofy stuff I realized was goofy as soon as I posted it )