How does Wilf's shadow ROM block swapping work?
Posted: Thu Aug 01, 2019 11:33 pm
Several of Wilf Rigter's designs use an improved memory decoder based on a 74HC251 multiplexer: Thanks for all the memories, ZX RAM I/O, ZX97 Lite. I'm puzzled by the switch that allegedly swaps the 8K block in the address space of 0-8K in ROM with the block in 32-40K in RAM.
If I understand it correctly, the multiplexing works as follows. The top three address lines are tied to the three binary inputs, representing a binary number from 0 to 7. This partitions the entire 64K address space into eight blocks of 8K each. The multiplexer also has eight linear selection inputs; each one therefore corresponds to an 8K block.
When a particular 8K block is being addressed, output Y is set to the logic level of its corresponding linear selection input; output W is simply set to the inverse value. Y and W then drive /RAMCS and /ROMCS, activating either the RAM or ROM chip for the address on the bus. So by assigning a low or high logic level to a given linear input, we can choose whether an address in that block will be picked up by the RAM or ROM. That's straightforward enough.
However, in order to swap blocks in the memory space, i.e. remap them, you'd have to adjust the address lines themselves. And according to the datasheet, the address lines are strictly inputs.
Perhaps only the roles of RAM and ROM are being swapped for these blocks: i.e. 0-8K ROM is swapped with 0-8K RAM and 32-40K RAM is swapped with 32-40K ROM. But that wouldn't be very practical, as you wouldn't be able to write into the 0-8K RAM space before the swap because the ROM is in the way. And it also doesn't fit the descriptions given in Wilf's and Rodney Knaap's ZX97L articles.
So, what's going on here?
If I understand it correctly, the multiplexing works as follows. The top three address lines are tied to the three binary inputs, representing a binary number from 0 to 7. This partitions the entire 64K address space into eight blocks of 8K each. The multiplexer also has eight linear selection inputs; each one therefore corresponds to an 8K block.
When a particular 8K block is being addressed, output Y is set to the logic level of its corresponding linear selection input; output W is simply set to the inverse value. Y and W then drive /RAMCS and /ROMCS, activating either the RAM or ROM chip for the address on the bus. So by assigning a low or high logic level to a given linear input, we can choose whether an address in that block will be picked up by the RAM or ROM. That's straightforward enough.
However, in order to swap blocks in the memory space, i.e. remap them, you'd have to adjust the address lines themselves. And according to the datasheet, the address lines are strictly inputs.
Perhaps only the roles of RAM and ROM are being swapped for these blocks: i.e. 0-8K ROM is swapped with 0-8K RAM and 32-40K RAM is swapped with 32-40K ROM. But that wouldn't be very practical, as you wouldn't be able to write into the 0-8K RAM space before the swap because the ROM is in the way. And it also doesn't fit the descriptions given in Wilf's and Rodney Knaap's ZX97L articles.
So, what's going on here?