What would you expect a high-z but pulled-up output to do to a data line?

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sirmorris
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What would you expect a high-z but pulled-up output to do to a data line?

Post by sirmorris »

So. I'm pulling my hair out trying to understand the behaviour of what I consider to be a quite trivial interfacing matter.

I have a GAL (20V8B) that is programmed to recognise to an IO read at a particular address. When the IO read is detected it enables a normally hi-z output and gates the logic level present at another input onto the data bus. A single bit, D7. With the D7' output connected to the bus the zeddy won't run.

The input conditions have been checked with a logic analyser and appear to be correct. As far as I can tell the output is actually hi-z. I've run tests on a breadboard which I think confirm this. I'm happy that the GAL logic is correct.

The GAL's outputs have an active pull-up. I can't control it, it's always on. My logic probe reports a logic high when I test the D7' output.

I wonder if the pull-up is a little too aggressive and it results in d7 always being pulled to logic 1.

What would the panel suggest I try next? Should I put a resistor in line? A diode? I'm lost, I have to admit :?
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1024MAK
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by 1024MAK »

If the GAL output is supposed to output logic 1 as well as logic 0, a diode in line is of no use. Unless you are going to rely on the bus "floating" high for the logic 1.

An in-line resistor (say 470 ohms to 680 ohms) may enable you to isolate if this is the problem.

The correct "full price" engineering solution would be for the GAL to drive a proper 74 series tri-state bus driver (assuming that the GAL can output both data and the bus-drive output enable).

Mark
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sirmorris
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by sirmorris »

At this point it's academic, I'd like to know why this doesn't work but I'm not willing to hurt my brain over it. It's an item in a long list of things I have to finish, and so in order to not delay the items rapidly approaching from behind I'm going with another solution. I only hope it doesn't suffer the same issues :lol:

I need an inverter and a three state buffer to gate a signal on to the data bus. I've got an HC125 that should do the trick.

For the inverter I'm going to do this:

Code: Select all

 A7 ---> !OE1
 5V --->  A1
!A7 <--+  Y1
gnd -=-+
The output Y1 will be pulled low with a 1k resistor. This means !A7 will be low when A7 is high because the output Y1 is in hi-z and pulled down. !A7 will be high when A7 is low because the output Y1 will be enabled thus driving output Y1 at 5V.

For the gate I'll do this:

Code: Select all

 !ENA -->|--+
!IORQ -->|--+
  !RD -->|--+--> !OE2
 BUSY --------->  A2
   D7  <--------  Y2
The three inputs will be diode-OR'd so that the output will be enabled only when all are low.

Simples! (Do people still say that?)

My only question here is whether I need the pull-down resistor on the diode OR array, as is commonly depicted. Some say yay, others nay. It's trivial to add one if needed I guess.
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1024MAK
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by 1024MAK »

Yes, you should include a pull-down resistor so that when none of the diodes are conducting, the HC CMOS input pin gets a definitive logic level. As you are using HC CMOS, the value can be say 10k ohms. But it does depend on the switching speed required. Use lower resistor values for faster switching.

Mark
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sirmorris
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by sirmorris »

Thanks Mark. I'll check the switching speed. What kind of lower limit value should I consider?
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1024MAK
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by 1024MAK »

Depends on what devices are driving it via the diodes. I would suggest that a normal minimum of 470 ohms to 1k ohms.

1k being typical for use as pull-ups when used with 74xxx or 74LSxxx TTL gates. Of course, the trade-off with a lower value resistor, is higher power consumption.

The reason that a lower value resistance is required at higher switching speeds, is a lower value resistor will discharge/charge the CMOS input gate capacitance (plus any stray capacitance) quicker.

Mark
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gammaray
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by gammaray »

I would expect hi-z state to be disconnected from bus. Data line would then be subject to state of collision?

But I don't anything about GAL's except that they are called "GAL". Educate me!

Charles
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1024MAK
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by 1024MAK »

Some devices have pull-up devices which are not able to be disabled even when the output is programmed to operate in tri-state (hi-z) mode :-(
In certain cases, this can load the line that they are connected to.

Mark
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sirmorris
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Re: What would you expect a high-z but pulled-up output to do to a data line?

Post by sirmorris »

GAL = Gate Array Logic - a now obsolete class of programmable logic device which allows the user to re-configure the internal configuration of 'macrocells' to perform arbitrary logic functions rather like how an EEPROM reconfigures bits to represent bytes. It's the predecessor to CPLD and FPGA, and somewhat comparable to a re-writable ULA.

They're very useful because they can combine the function of a number of discrete TTL devices. This can lead to reduced power consumption and easier routing. As the inputs are arbitrary you can design the fan-out to more closely match the requirements of your board.

In this case however, as Mark correctly points out, the HI-Z function of the pin is somewhat spoiled by having an over-eager pull-up which is not user controllable. It's loading the bus and causing the zeddy to not boot :x
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