Create ULA for €5?

[mrtinb]

When looking at the different solutions for a ULA in this thread, I came across these cheap parts that might work together for at ULA replacement.

A Xilinx XC9536, that works at 5V: €3,87

A PLCC44 to DIP40 adapter board: €1,36

The sum of this hardware is: €5,20

It also depends how the pins on the adapter board is mapped. (Assumably connected like this). Looking at this diagram, GND and 5V will not match the ULA.

You will probably need a JTAG-kit like this one (€25,04) to program the CPLD.

I'm just trying to think out of the box.

[PokeMon]

I think it won't work with a 44 pin CPLD which has only 34 I/O pins. Also I doubt that 36 macrocells will be sufficient for this purpose. The ULA is quite complex. XC9536 won't be manufactured in PLCC version as well (end of life product). There maybe some sources but not a good idea to base a new product on EOL parts.

Bildschirmfoto 2016-10-24 um 10.53.36.png (108.54 KiB) Viewed 9578 times

As there are implementations existing, why not use the proofed solutions ? I think you won't be able to avoid soldering SMD parts for these kind of solutions.

[Andy Rea]

Karl is right regardless if the design will fit in that amount of logic with only 34 i/o pins it's not gonna happen, i tried a 2 chip solution but couldnt get it to work stable enough using an altera epm7032stc44 ( a quad flat pack 44 pin device) witoutn enough IO but used and additional 16v8 Gal to grab the databus and drive the address lines. but meh thats another story.

Andy

EDIT :

you could use this http://www.ebay.co.uk/itm/IC-EPM7128SLC ... 51d6aa3d84 mpt as small but should work.. and cheap enough

[mrtinb]

I think it won't work with a 44 pin CPLD which has only 34 I/O pins. Also I doubt that 36 macrocells will be sufficient for this purpose.

Upgrading the design from a XC9536 to a XC9672 would solve this. And then I realize it has already been done by RetroTechie’s ZX81 ULA in a CPLD.

Doh!

It's still a cheap project:

• DIP 84 PLCC €0,76
• XC9572 €4,54

I'll look into a strip board or perfboard design for simplicity and price cut.

[Andy Rea]

that seems awfully cheap for the XC9572 are they NOS or pulls ?

regards Andy

[mrtinb]

No idea. I just searched a cheap Chinese site.

[mrtinb]

The chips have been ordered from China (will probably arrive in 2 months).
Now I'm trying to install Xilinx' 16GB software to learn how to create circuits there.
Next: import RetroTechie's design.

[mrtinb]

I've started to setup RetroTechie's circuit in Fritzing.

Project:

• Buy cheap components as listed above
• Make single sided print that can be produced by anyone
• The XC9572 can be programmed with an Arduino (which is a lot cheaper than buying a JTAG-programmer for €25+)

plcc84.2_pcb.png (127.47 KiB) Viewed 9457 times

plcc84.2_schem.png (110.31 KiB) Viewed 9457 times

(I've seen now you can etch with lemon juice, salt and hydrogen peroxide (Wasserstoffperoxid), so now dangerous chemicals aren't needed anymore)

(Edit: And I found you can transfer toner to pcb without iron)

[mrtinb]

It's quite a job to create this with a single sided PCB. Yet only half the connections are made.

plcc84.3_pcb.jpg (264.03 KiB) Viewed 9298 times

(Edit: updated image showing further progress)
(Edit2: updated image showing further progress)
(Edit3: updated image showing further progress)

[RetroTechie]

I've started to setup RetroTechie's circuit in Fritzing.

Arghhh... Friends don't let friends use Fritzing. Especially not for pcb layout. There's some (limited, imho) purposes for this program. But for laying out pcb's, literally any pcb layout software out there is better suited. Try Eagle, or Kicad, or ..., ...., ....

Some tips:
* Double sided board makes layout much easier.
* Any signal that goes to a regular CPLD I/O pin, can be swapped with another I/O pin on the CPLD. Yes, you'd need to re-do the synthesize ('compile') CPLD design step. But that isn't as hard as you might think. Swapping pins means you can basically lay out most traces nicely next to each other as you want.

Strictly speaking, swapping pins may influence timing. And not any desired pinout may be possible in the first place. But in practice, this isn't much of an issue, and you can try in ISE before actually doing a pcb layout or configuring the CPLD.

Basically: 1) Lay out traces in the easiest/simplest manner. 2) Feed that pinout to ISE, and re-do the synthesize step(s). 3) If that doesn't work & a few pins are changed (or need changing), repeat those steps in ISE. 4) Use 'ISE-approved' pinout to finalize the pcb layout.

Sticking to a CPLD pinout that I once used for a pcb layout I did in a way you wouldn't want to repeat anyway, just makes your job harder than it needs to be.