ZX81+35 Clone

[mahjongg]

Well, yes, its the old logical rule that inverting both inputs and outputs turns an OR into and AND and vice-versa, I use that extensively in my designs.
For example originally I had planned to use 4-input ANDs for the VSYNC and /PORCH, but I saw that most of the AND inputs were active LOW, and it would have taken six or so inverters to solve that, so I simply used a 4-input NOR instead, using the above rule.

If you look at official PAL/NTSC video/sync patterns you will see that during the long vertical sync horizontal sync pulses are inserted as inverse HSYNC pulses so as to keep the hsync generator running, (I assume) so sometimes an exclusive OR is used to replicate that, the problem with that is that the Hsync pulses are not in the right position, as the ZX81 does NOT produce an interlaced picture. Some TV's have trouble with that, leading to jerking of characters on the top as the hsync generator is out of sync at first. Simply leaving the hsync pulses out during the long vertical sync seems to solve that problem.

[PokeMon]

Yes - Andy is right, /hsync and /vsync must be ANDed.
I think that's why his name is ANDy.

About the frame coding - in principle you are right but for the correct coding you have to repeat these pulses every 32us not every 64us and one pulse must be suppressed. And the length of the sync pulses differs with 2.3us versus 4.7us. So I would avoid this because this is more complex and a wrong attempt (with wrong timings) could irritate TVs and mark the signal as invalid.

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[mahjongg]

Yes, that is why I stated

the problem with that is that the Hsync pulses are not in the right position, as the ZX81 does NOT produce an interlaced picture.

But thanks for the detailed explanation. Main reason for making it possible to use an XOR was that I simply wanted to see what the effect is in practice, but I agree it probably won't be an improvement.

combinatorial logic for /csync is that /csync is low as either /hsync is low OR /vsync is low, meaning I have need two active low input signals, and an active low output signal

so we need /hsync AND /vsync for /csync but in my schematic I'm using one inverted and one none inverted input, meaning that I cannot use a simple port.
I will change it to having two active LOW inputs, and change the port to an AND.
P.S. edited out some errors in my text.

[mahjongg]

Looking what is available in single gate logic (preferably in a SOT23-5 package), and the cheapest device, I come out at the 74HC1G08 AND port, when using active low (/VSYNC and /HSYNC) inputs and and active low output /CSYNC
Meaning, the output is low if either /VSYNC or /HSYNC is low.

Will change the schematic accordingly

[mahjongg]

@pokemon,

you asked about the turbo circuit, it actually based on wilf rigters bare bones turbo circuit http://www.user.dccnet.com/wrigter/inde ... /turbo.htm at least the clock doubler part of it is. The turbo latch is controlled so that the turbo is turned automatically while the Z80 is "executing" the video file, which must be done at slow speed, or the line length would halve too (if the video generator logic could keep up, which I somewhat doubt).
at the same time the turbo circuit (clock doubler) circuit is active, I also activate a change is the wait generator circuit that should give a 10% speed boost. With a manual controlled switch you can switch between "normal" speed and boosted speed.

[PokeMon]

Thanks, I saw this at the second view after your hint with the switch.
And what is about the speaker output ?
I did not see an AY chip on the schematic.
Maybe you can leave explanations about it.

[mahjongg]

Well, yes, the speaker output..
I decided I wanted the barest minimum I/O expansion to give my clone some general purpose I/O, so I created one 8-bit output latch.
Initially I wanted only a simple clicker 1-bit audio output, and yes I realize that generating any sound beyond perhaps a simple key click would mean you have to stop video generation, There is a reason a ZX81 does not support sound. It is virtually impossible to create any software driven sound while generating video.
But I would be possible to stop video, play a simple melody, then continue generating video.
Having added 8 output bits I decided that probably the most useful use for it (one that also defined the layout of the GPIO header) would be to control an LCD interface with it, so I created a header with the pins in the right place to support a simple 16 character 2-line text LCD. the idea was that you could drive the LCD, but (at the same time) you could also use the four bits used for the LCD nibble data for something else, when not sending data to, or not using the LCD, so I made a simple 4-bit ladder DAC for audio (so you can generate polyphonic sound). I had one left over pin from my 14-pin connector, and decided to use the one spare input bit from the keyboard input to it, so the "GPIO" port would have at least one input bit.

when my ZX81 clone proves to be working I will try to create a few expansion boards for it, probably the first one will carry an AY-3-8910 chip.

by the way the problem with accessing the Revspace web site has been solved.

[1024MAK]

@ mahjongg, the chip that feeds the GPIO header is shown as a 74HCT541 (U30) which is a buffer/driver, not a latch. But the note on your schematic says "latch". So I was wondering if you have an LCD that is fast enough, given you also have a turbo mode.
Also, if you are intending to use a latch for this position (U30), are you relying on well written software to keep the audio quiet (send data to the LCD, then immediately send zero to prevent clicks on the audio)? As another resistor and NPN transistor (connected to one of the GPIO output data bits that the LCD does not use) could be used to mute the audio if you wished.

Mark

[mahjongg]

Darn! you found another design error, obviously I intended U30 to be a latch, but copy/pasted the wrong chip. It should have been another 74HC574, I don't understand I didn't see that, must have overlooked it a hundred times. I'm very happy you found that, thanks!

as for audio during writing to the LCD, I did not intend to both use the LCD and play audio at the same time, but yes when writing data to the LCD there will be audio generated if you use both LCD and audio logic, I don't see that as a big problem, in fact I wired the audio to a PIN of the header that isn't used for the LCD, so its not the intention to connect both an LCD AND the speaker.

I created a new schematic (.PDF) and posted it at Revspace. It fixes both the AND port for /CSYNC, and the latch for U30.
I will create a .PNG picture version tomorrow, and post it here and at revspace.

please keep looking for other errors!

[mahjongg]

Well I found a .PDF to .PNG online converter, so I don't have to wait until tomorrow to convert the .PNG at work, so here it is:

ZX81+35 REV 2.2-1.png

ZX81+35 REV 2.2

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