Andy, do you mean the Maskable interrupt generated when bit 6 of R register changes from 1 to 0?Andy Rea wrote:is there a way to contact the author
his hsync counter is resetting on the vsync, which of course is wrong
it should only reset with an int-ack and then the hsync is generated 16 clock cycles later
Doing it any other way may work, but probably will result in timing differences (depending on software used). Read: may look okay at first glance, but not 100% ZX81 behaviour upon closer inspection.
That would be because Z80's /INT line is hard-wired to the A6 line in a ZX81. Other than how this affects software: unrelated to the above.chernandezba wrote:Andy, do you mean the Maskable interrupt generated when bit 6 of R register changes from 1 to 0?
Spotted this project a while ago. Looks like it's getting along nicely...
Hi AndyAndy Rea wrote:is there a way to contact the author
I contacted them (tried my Dutch after all these years again).
Waiting for an answer now.
kind regards Paul
-when bit 6 of r register changes from 1 to 0, a maskable interrupt is generated. Then, as Andy says, a hsync is generated after 16 cycles of the int ack. So, if we are in a loop changing r register to a constant value, for example 0, the interrupt will never be fired and never will be generated a hsync? So the hsync is not fired at a constant interval?
-the other question is related to nmi... When it is fired? At the end of every scanline, at fixed 207 cycle interval?
Or it depends on the hsync? In the last case, it will depend on when the maskable interrupt is fired and the two types of interrupt would be fired almost at the same time...
The NMI is touched with every hsync pulse (synchronous). You can switch off the NMI but not the hsync.
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signal (INT) with the rising edge of the final clock at the end of any instruction. The
signal is not accepted if the internal CPU software controlled interrupt enable flip-flop is
not set or if the BUSREQ signal is active. When the signal is accepted, a special M1 cycle
is generated. During this special M1 cycle, the IORQ signal becomes active (instead of the
normal MREQ) to indicate that the interrupting device can place an 8-bit vector on the
data bus. Two wait states are automatically added to this cycle. These states are added so
that a ripple priority interrupt scheme can be easily implemented. The two wait states
allow sufficient time for the ripple signals to stabilize and identify which I/O device must
insert the response vector.
so the int-ack is the signal M1 = low and IORQ = low at the same time,
hope this helps