I was not totally satisfied with v1: three gates were left unused, and it did not have a way to shadow the ROM with the RAM (there was already the two banks EPROM feature, but erasing the EPROM and reprogramming it each time you want to test some new ROM code is rather tedious)...
Well, here is v2.00, with ROM shadowing (tested and working) !
The shadowing feature works as follow: when not in shadow mode, all writes to the ROM addresses (0 to 8191) are redirected to the RAM (same address), but all reads are still performed from the ROM; I.e. you can copy the ROM contents into the RAM with a simple:
Code: Select all
10 FAST
20 FOR I=0 TO 8191
30 POKE I, PEEK I
40 NEXT I
50 SLOW
Then you can patch the copied ROM code at your leisure, still with POKEs (or machine code LD, of course).
Once you are happy with your patched ROM image, you can flip the shadowing mode on (with an external switch wired to the SL3 connector of the board: it doesn't even crash the ZX81 !
), and then your ZX81 runs the shadowed code from the RAM instead of the ROM (it keeps however using the ROM characters table for producing the video, so you can't patch the character set, but on the other hand, you can reuse the last 512 bytes of the ROM addresses it occupies in the shadowing RAM to store any machine code routine you fancy.
In my first draft of v2.00, the RAM was kept read/write while shadowing the ROM, but I still had one AND gate left unused, and I told to myself that it'd be better to write-protect the RAM once the shadow mode is in force, to prevent getting its contents accidentally corrupted in case of crashes... So, in the final version, I added a jumper to choose between the two modes: read/write shadowing RAM or read-only while shadowing (and of course still write-enabled when not shadowing the ROM).
You will also notice that I replaced the jumper used for choosing the EPROM bank in v1.10 with a pull down resistor and a two pins connector (for hooking an external switch to it). When SL4 pins are left open, the lower 8K bank is selected in a 27C128, while when shorted, the upper 8K bank is used.
If you are using the original ROM on the board (reminder: I could not test a ROM since mine is dead, so there's no guarantee it would work; see my comments in v1.10's post, about ROM and RAM timing discrepancies), then simply place a jumper on the SL4 connector pins (a switch is useless). For a 27C64 (8K) EPROM, you can simply let the pins unconnected (it doesn't matter).
Here is the new schematic:
Since I didn't want to redo the whole shebang, I kept more or less the same layout, but with a slightly better routing (with the first draft, the board even had one less strap than v1.10...). Alas, the write-protecting addition is almost impossible to do in a "clean" way (i.e. with just normal straps); too many straps would have to be added, which in turn would cause the board to become too small to fit them all between the ICs. So you'll notice that two (insulated) wires are to be added on the solder side of the board (from pin 1 and 2 of IC1 to pins 10 and 9 of IC2), which prevents having to use a double-sided board.
So, here is the final layout I adopted (and built):
Note that in addition to the CPU signals brought to the v1.10 board, you'll also need to bring the ~RD signal (which was added to the SL1 connector).
I replaced SL2 with a 5 pins connector, but if you already wired a v1.10 board with a 6 pins connector, you can reuse the latter as well (there's an additional hole+pad, next to SL2, for this purpose); note however that pin 1 of SL2 is now connected to the ground (it was connected to +5V in v1.10): the 2Kb RAM blocks in the 8-16K region are enabled when the corresponding pins are grounded (or when the corresponding switch on the S1 DIP switches block is ON).
And here is a PDF file with the printed circuit tracks, ready to print:
