Custom 64K RAM expansion for the ZX81

[dinosaur]

Greetings,

I've been trying to build my own RAM expansion. The RAM CS and ROM CS generations are based off the following logic: http://home.comcast.net/~kr.baker/zx81_64k.gif.

Did anyone got the latter to work ?

[Rishi]

Keep me updated on your progress, the /RAMCS in this schematic seems to refer to /CE on the SRAM, if you're putting it on the edge, then /RAMCS should always be high, (A16 on the RAM either high or low, but consistent) /REFSN could also be wired in with /RD, it should effectively give you 56K RAM. See the other thread on Bad-memopak and my troubles. My advice, make sure you have all you want included in the plan when you start soldering stuff up. test everything on a breadboard first (i suppose you could already connect A0-A14 and D0-D7 permanently, but if you want UDG, figure how you want to have the resistor-bridge, if you're considering an IO-port, make an extra input on the /CE, and i personally think the ROM-ghost is pretty cool, but it does require some special switching.

[nollkolltroll]

Yes, I used to have that expansion working in one of my ZX81:s. RAMCS and ROMCS are the newly decoded signals required for the ram & rom chips, the old RAMCS and ROMCS are not used any more.
I ditched this expansion and built a 16k internal RAM that does WRX, and also an 8k in the 8-16k area that can do UDG. Much more fun!

[RetroTechie]

Had this particular circuit in my archives for a loooong time, and it looks like a good circuit to me (haven't tried it though). 2 remarks:

• If you unsolder only the ULA side of R28 / R2 (leaving the other side in the board), and connect /ROMCS and /RAMCS from this circuit to the just-unsoldered side of each resistor, then external ROM or RAM packs should work as expected.
  I'd prefer that over putting the outputs of this circuit directly on the edge connector: "Make sure you don't attempt to use a RAMpack after you make this mod." - yeah right, good luck with that.
• It wouldn't surprise me if -with a bit of effort- you could cut this circuit down to 2 pcs 74xx IC's rather than 3.

[dinosaur]

Well, your confirmations encouraged me to further hunt down the bugs in the board I created (started working on it on Thursday, finished the routing on Saturday and double checked stuff, then etched the board and soldered everything on Sunday... Just to discover it was not working).

I had already found one bug when I posted my first message in this thread (didn't read carefully enough the 6C1008 datasheet: CE2 is active high, not low, unlike CE...) and corrected it (that was the easy bug), but to no avail... So I started to wonder if the logic circuitry itself was valid for a ZX81 (I've seen quite a few different designs, some involving RD in the ROMCS/RAMCS generations, unlike that one).

So, I checked my wiring once again today, and bingo !... I had mistakenly attached pin 24 (which carries +5V) of the RAM (as shown on the ZX81 schematic, i.e. pin 26 of the 28 pins socket... still following me there ?.... ) to an address line of the RAM and left pin 22 floating (i.e. I inadvertently wired the two pins the wrong way around). Once this error corrected, everything works fine and as expected !

The conclusion I drew from this is: when you got three different reference layouts (24 pins chips ZX81 schematic + 28 pins mod on the ZX81 board + 32 pins SRAM), quadruple check your work !


Here is my board: 64K RAM (in fact even twice that amount, since the 6C1008 is a 128Kb SRAM), 56K of which are actually used, with individual enabling of 2Kb RAM blocks in the 8-16K address range (so that you still can plug extensions making use of those address ranges without conflict). The RAM is software-HRG compatible (not Memotech module HRG compatible however !).
The board also carries a socket for the ROM or an EPROM (any EPROM from a 27C64 to a 27C512 can be used), and in the case of an EPROM, two banks (for 27C128 and above) can be chosen from (i.e. the last 16Kb of the EPROM are split in two banks and you can select any as the ZX81 ROM space).
It is suited for re-boxed ZX81s (I got mine boxed inside an Indescomp box+keyboard) and fits directly onto the ZX81 board, piggy-backed onto the ROM and RAM 28 pins sockets (i.e. you must remove the old RAMs and fit a 28 pins socket in their place, and also wire the LK2 strap: this setting still allows you to use the ZX81 without the board, but with a 6116 plugged into the "lower" part of the 28 pins socket, giving you a 2Kb ZX81); the reason for this choice is that I was totally fed up with the Memotech Memopack and HRG modules which kept wobbling into the card edge socket and crashing the ZX81 at the slightest hit on the box. Now, with that piggy-back method, I can hit and shake the box as hard as I want, and it doesn't crash !

Attached are the pictures. You'll see the two corrections on the underside of the board.

[dinosaur]

And here is the v1.10 schematic and layout for the board, if someone is interested in building one.

It got the bugs fixed and a better layout (with only 8 straps).

Note that there's a slight gotcha: you need a fast EPROM (150ns or better: I am using a 120ns one), else you risk having black characters and/or vertical stripes on the display; this happens when the RAM and the ROM have large cycle time discrepancies (in fact, the EPROM I'm using on the board was too fast and didn't work properly with the original RAM, when plugged onto the bare ZX81 board, and I had to use a slower (250ns) EPROM: with the RAM board, it's the other way around). So, I cannot guarantee that the original ZX81 ROM would work either (I couldn't test it, because my original ROM forgot its contents in the last 30 years or is simply dead).

As for the wiring, you'll need to bring, via the SL1 connector the ~MREQ, ~M1, A15, A14 and A13 signals: I recommend doing like I did, soldering the wires directly on the Z80 corresponding pads, on the underside of the ZX-81 PCB.

You may use the SL2 connector to wire switches accessible from outside the box, so to enable and disable the corresponding RAM blocks easily (in this case, simply let the corresponding S1 dip switches open, and wire your switches so that they pull the line at +5V when enabling the RAM corresponding block.

JP3 allows to choose the EPROM bank, when the said EPROM is larger than 8Kb (27C128 to 27C512). For the ZX-81 ROM, this jumper must have its positions 2-3 shorted.

JP1 and JP2 must be positioned accordingly to the type of ROM in use (position 2-3 shorted for the original ROM, 1-2 for any EPROM).

Oh, I almost forgot: the layout is for an issue 3 ZX81 board !

[Rishi]

Very... Nice... Work !

[sirmorris]

Nice!

[dinosaur]

I was not totally satisfied with v1: three gates were left unused, and it did not have a way to shadow the ROM with the RAM (there was already the two banks EPROM feature, but erasing the EPROM and reprogramming it each time you want to test some new ROM code is rather tedious)...

Well, here is v2.00, with ROM shadowing (tested and working) !

The shadowing feature works as follow: when not in shadow mode, all writes to the ROM addresses (0 to 8191) are redirected to the RAM (same address), but all reads are still performed from the ROM; I.e. you can copy the ROM contents into the RAM with a simple:

Code: Select all

10 FAST
20 FOR I=0 TO 8191
30 POKE I, PEEK I
40 NEXT I
50 SLOW

Then you can patch the copied ROM code at your leisure, still with POKEs (or machine code LD, of course).

Once you are happy with your patched ROM image, you can flip the shadowing mode on (with an external switch wired to the SL3 connector of the board: it doesn't even crash the ZX81 ! ), and then your ZX81 runs the shadowed code from the RAM instead of the ROM (it keeps however using the ROM characters table for producing the video, so you can't patch the character set, but on the other hand, you can reuse the last 512 bytes of the ROM addresses it occupies in the shadowing RAM to store any machine code routine you fancy.

In my first draft of v2.00, the RAM was kept read/write while shadowing the ROM, but I still had one AND gate left unused, and I told to myself that it'd be better to write-protect the RAM once the shadow mode is in force, to prevent getting its contents accidentally corrupted in case of crashes... So, in the final version, I added a jumper to choose between the two modes: read/write shadowing RAM or read-only while shadowing (and of course still write-enabled when not shadowing the ROM).

You will also notice that I replaced the jumper used for choosing the EPROM bank in v1.10 with a pull down resistor and a two pins connector (for hooking an external switch to it). When SL4 pins are left open, the lower 8K bank is selected in a 27C128, while when shorted, the upper 8K bank is used.
If you are using the original ROM on the board (reminder: I could not test a ROM since mine is dead, so there's no guarantee it would work; see my comments in v1.10's post, about ROM and RAM timing discrepancies), then simply place a jumper on the SL4 connector pins (a switch is useless). For a 27C64 (8K) EPROM, you can simply let the pins unconnected (it doesn't matter).

Here is the new schematic:

ZX81_64KRAM+ROM_schematic_v200.png

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Since I didn't want to redo the whole shebang, I kept more or less the same layout, but with a slightly better routing (with the first draft, the board even had one less strap than v1.10...). Alas, the write-protecting addition is almost impossible to do in a "clean" way (i.e. with just normal straps); too many straps would have to be added, which in turn would cause the board to become too small to fit them all between the ICs. So you'll notice that two (insulated) wires are to be added on the solder side of the board (from pin 1 and 2 of IC1 to pins 10 and 9 of IC2), which prevents having to use a double-sided board.

So, here is the final layout I adopted (and built):

ZX81_64KRAM+ROM_layout_v200.png

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Note that in addition to the CPU signals brought to the v1.10 board, you'll also need to bring the ~RD signal (which was added to the SL1 connector).

I replaced SL2 with a 5 pins connector, but if you already wired a v1.10 board with a 6 pins connector, you can reuse the latter as well (there's an additional hole+pad, next to SL2, for this purpose); note however that pin 1 of SL2 is now connected to the ground (it was connected to +5V in v1.10): the 2Kb RAM blocks in the 8-16K region are enabled when the corresponding pins are grounded (or when the corresponding switch on the S1 DIP switches block is ON).

And here is a PDF file with the printed circuit tracks, ready to print:

ZX81_64KRAM+ROM_board_v200.pdf

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[1024MAK]

Not had time (or brain power) to study it yet, but looks good

Well done

Mark