ZX81 Hi-Res

[britain4]

try connecting a 33pf capacitor across GND and RAM-CS ( i think its pin 20 but not sure) at the ram chip.

regards Andy

I've just tried it, didn't make any difference I'm afraid - we might just have to see how it goes with a different chip!

Cheers

interesting i had the same problem years ago, and when putting a scope probe on the CS pin it would work, and removing the probe the artifacts would re-appear so putting the cap there reproduced the capacitive loading of the scope probe.

oh well was worth a shot. hope you sort it.

regards Andy

Just thought I'd give you all an update on this as it's fixed!

I tried a few different Z80 chips - the CMOS one gave the result shown in the pic I posted, all of my NMOS ones gave the same result as each other with about half the number of artefacts visible.

So I tried the suggestion of a cap over the GND and RAM-CS pins as suggested with the NMOS chip and it now works beautifully.



Thanks everyone especially Andy for the suggestion of the cap!

I guess it sucks I can't use my nice cool Z80 but I'm just pleased it's working

[Andy Rea]

Glad you got it working, i believe the root of the cause is that newer parts have much faster slew rates on there outputs, so the older ram chips work maintain their output for a fraction longer than the newer ones, by adding the cap to the chip select we are keeping it enabled a fraction longer.

Regards andy

[britain4]

Glad you got it working, i believe the root of the cause is that newer parts have much faster slew rates on there outputs, so the older ram chips work maintain their output for a fraction longer than the newer ones, by adding the cap to the chip select we are keeping it enabled a fraction longer.

Regards andy

Thanks. I had a feeling it had to be something vaguely along those lines.

Not the end of the world I can't use the CMOS chip anyways and I'm just glad it works. Thanks again!

[mikeh_nz]

FYI

For my internal 16KB, where the chip is a CY62256-70 (and the original Zilog Z80A), I ended up having to increase the capacitor to 100pF before the screen artifacts would go away.

I was pleased to find a nice spot on the issue 3 board to place the cap between CS & GND

Nice spot for the cap on issue 3 board.

[Mustermann]

If I understood right, this is a classical race condition.

ULA load shift register at the falling edge of T4 cycle. /MREQ go to high at the same time.

So this is working with the original slow ROM and very slow RAM.
With fast RAM the data is invalid prior ULA is reading it. So you need to delay /RAMCS.

Adding a cap is building a RC gate that delay the signal. Faster the RAM need more delay so the cap increase.

Any non inverting gate in line would work as well.

Building /RAMCS from NOT A14 || /MREQ && /RFSH is the standard solution for HRG using SRAM.
Doing so RAM stay enabled until end of T4 cycle.

[1024MAK]

Any non inverting gate in line would work as well.

Or using two inverting gates.

But adding a capacitor is definitely the easiest method if doing the simplest internal RAM upgrade.

Mark

[mikeh_nz]

I have a second zx81 that I’m struggling to remove the artifacts on.

I’ve tried swapping the cpu with the other while a 33pF attached, and no change to how the artifacts look. So I think it isn’t the cpu.

For the non-inverting gate - you mean like AND or 2 NOTs between the memory chip’s /CS pin and the socket?

Building /RAMCS from NOT A14 || /MREQ && /RFSH is the standard solution for HRG using SRAM.

Can you add some ( ) to indicate the correct evaluation order? Would this work too on internal memory?

I assume NOT A14 || ( /MREQ && /RFSH )

And you are saying CS becomes active (ie low) when A14 selected AND (MREQ active OR RFSH active OR both MREQ&RFSH active)

[1024MAK]

For the non-inverting gate - you mean like AND or 2 NOTs between the memory chip’s /CS pin and the socket?

One non-inverting buffer, or one AND gate with both inputs connected together, or one OR gate with both inputs connected together, or two inverters (NOT gates) connected in series, or two NAND gates connected in series or two NOR gates connected in series etc…

Yes between the /RAMCS from the ULA and the /CS pin of the RAM chip.

Building /RAMCS from NOT A14 || /MREQ && /RFSH is the standard solution for HRG using SRAM.

/CS low on the RAM required when A14 is high (Z80 addressing RAM, so address decoding) AND either /MREQ low (Z80 accessing memory) OR /RFSH low (Z80 performing a memory refresh cycle - used by the video system).

A14 is low when the ZX81 is accessing ROM. A14 is high when the ZX81 is accessing RAM.
If both /MREQ and /RFSH are high, the RAM should not be active.

Mark

[mikeh_nz]

Thanks for the insight.

It seems like the logic gate would just add delay, but the computing of /CS from the other signals might keep /CS active for the correct period?

[mikeh_nz]

Well I've tried

1. 1 OR gate (tied together)
2. 2 OR gates in series
3. 3 OR gates in series

and all produce the same artifacts in the high res mode.

Artifacts with 3 ORs in series

Setup with 3 ORs in series

Then I recomputed the /CS from (NOT(A14) OR (/MREQ AND /RFSH)) - exactly same artifacts

Exactly same artifacts when recomputing /CS from A14,/MREQ,/RFSH

Setup when recomputing /CS from A14,/MREQ,/RFSH

Thankfully I have my brothers ZX81 so I can swap things around to try and figure out what's causing this. But Im going to try that another night.

Earlier I've swapped the CPU earlier and didnt notice any change. I'll try that again with this setup and also swap the OS ROM.
That would leave the RAM chip and the ULA. I could try a different RAM chip.

My ULA is pretty old (datecode 8119). Sadly, its not socketed in this issue1, but is on the brother's zx81

Im guessing its going to be the ULA. Thoughts?