The ULA switches between NMI generated syncs and software triggered syncs immediately before the top line. If this sync timing is not exact then the issue that you see here will appear.
This points to the ULA as being the centre of this issue. It seems the heat is causing the triggering to be off (it only needs to be tiny to see a problem on the screen) - maybe the edge triggering has slipped slightly causing it to be delayed until the next internal clock signal. Just one clock cycle mis-match causes a disruption.
The remainder of the screen is then synced to the software triggered syncs, so the screen re-aligns.
The NMI signal matches the SYNCs so the NMI signal to the CPU could have a bit of a slope on it, again causing the trigger to be missed by one clock cycle.
I know because I had similar issues when implementing the NMI converter for the ZX80
Old version of the NMI, with some details of timing causing disruption here:
http://home.micros.users.btopenworld.co ... rsion.html
My new version has replaced the complete HSYNCS so that no disruption can occur.
http://home.micros.users.btopenworld.co ... 80nmi.html
Grant