Sam-Can wrote: ↑Sat Jul 03, 2021 5:05 pm
What I've understood so far:
[1] By preventing the RAM pack from connecting /RAMCS' to +5V is that the A14-based determination (0=>ROM, 1=>RAM) sent from the ULA is allowed to reach the onboard 1K RAM. Because otherwise if the RAM pack +5V were allowed, this would "over-rule" the /RAMCS' signal at the 1K RAM although wouldn't damage the ULA because of the 680 ohm R2 resistor. In summary: no RAM pack => ULA signal drives onboard /RAMCS, RAM pack => it over-rules the /RAMCS holding it high preventing the onboard RAM ever getting selected.
The ULA also includes the Z80 /MREQ signal in its logic for the /RAMCS, but otherwise correct
Sam-Can wrote: ↑Sat Jul 03, 2021 5:05 pm
[2] Typical (UK model for this description) onboard RAM is 1K, which lies from $4000..$43FF. That requires 10 bits of decoding A9..A0 at a minimum, and the ZX81 main board does not decode any other lines. For example, the onboard RAM isn't attached to A10. Consequently if A10 were 1, such as with the address $4400, then the limited decoding results in this addressing ($4400 & %010000111111111) = $4000.
Yes.
Sam-Can wrote: ↑Sat Jul 03, 2021 5:05 pm
So now this makes me wonder whether some "add-on" logic to the RAM pack might solve this:
[-a-] Supposing one were to detect (A14 AND (((A10 OR A11) OR (A12 OR A13))) and feed that on to /RAMCS', rather than just the straight connection to 5V. My thinking here is that if any address [$4400..$7FFF] (and presumably its ghost [$C400..$FFFF] since I'm not decoding A15 were to be put on the address bus, the /RAMCS' line would be asserted high thereby disabling the onboard ROM.
[-b-] However any address outside of that range would err
Thinking about it, I'm not sure whether that's ideal since in the case of that OR clause being 0, I really want /RAMCS out of the ULA - note the lack of ' i.e. the value before the resistor. Uh oh, my lack of electronics is showing
How and if, you further divide up the memory decoding depends on your objective.
For Sinclair, the objective was the lowest cost design, keeping in mind that the ZX81 ULA chip is basically is all the logic from the ZX80 plus a bit more in one chip. Hence partial decoding is used because it costs less. The result is that the ULA
ONLY considers address line A14 from the Z80. And the 1K byte RAM chip only has ten address lines. All the remaining address lines (A10, A11, A12, A13 and A15) are ignored. This gives the ZX81 a 32K byte area where the Z80 can read or write to it, even though it is only a 1K byte chip. This is what makes it so easy to upgrade the internal RAM to 16K bytes
In normal use, there is no point in tidying up the decoding by including address lines A10, A11, A12 and A13 into the decoding logic, because it makes no difference. Furthermore, A15 can’t easily be included in the decoding, because the video system relies on the ‘echo’ / ‘shadow’ of the RAM being in the top quarter of the memory map (49152 or 0xC000 upwards, A14=1, A15=1).
Hence the decoding works like this:
Code: Select all
A15 A14 Memory
0 0 Internal ROM
0 1 Internal RAM
1 0 Internal ROM
1 1 Internal RAM
However, if you want to attach extra memory or some memory mapped input/output hardware, then the external device has to include some address decoding circuitry to disable either the internal RAM chip (regardless of what capacity it has) and / or the internal ROM chip (which is also partly decoded, if you PEEK 32768 (0x8000) onwards, you will find it returns the same values as 0 onwards, A14=0, A15=0 or A15=1).
This disabling for RAM can be continuous, that’s why 16K RAM packs connect /RAMCS to the +5V supply. Or logic can selectively control either /RAMCS and / or /ROMCS.
If you look at the topic I linked to earlier, you should find a link to download a schematic circuit diagram of the single logic chip and a diode that is needed to move your 16K RAM pack and remap it in the 32768 (0x8000) to 49151 (0xBFFF) range (A14=0, A15=1). To do this, it adds some logic to control /ROMCS. By doing this, it overrules the ULA to ROM control. And hence allows the Z80 to access the external RAM pack without the two different memory systems fighting one another (which is called bus contention).
Mark