http://www.zx81stuff.org.uk/zx81/genera ... 4KRom.html
Both chips ("new rom" and "new ram") are addressed in the 8-16 K region. This region holds also a "mirror" of the BASIC rom. So the BASIC-ROM chip select line /ROMCS must be forced high on any access at the new rom/ram chips above 8K.
LOL i should have read page 2 before posting !!!!
Glad to rejoin the zx81 community!
While waiting to be activated, I peeked around past postings and started doodling up some circuit ideas. So here is a small contribution to the discussion of decoding the ZX81 memory space between 8K-16K for the specific memory chips mentioned (6116 and 2732) using Andy's 138 decoder drawing as a starting point. Note I switched the 74LS138 decoder to a 74HC138 part to reduce power and input current. Also note how A13 high is buffered by the NPN transistor to disable the ZX81 ROMCS line. Always be careful of bus conflicts on the ROMCS line if other memory decoders on the ZX81 expansion bus control ROMCS with an active low signal.
Having drawn this little circuit, I must say that the 6116 and 2732 memory chips were long ago superseded by denser and lower power memory chips are more readily available now. First of all I would simply replace the 6116 with a 62256 SRAM and the 2732 with a 27C256 EPROM. Then I would add a simple software controlled bank switching circcuit to select up to sixteen banks of 4K bytes each that can be switched "on the fly".
- single chip internal non-volatile 8K SRAM upgrade between 8K and 16K
- (133.37 KiB) Downloaded 3001 times
In the previously posted ZX RAMPAGERv1 schematic there is a problem with timing of memory access during the time that RFSH is low while MREQ is high. This short interval is important as the video pattern datat is fetched from ROM or SRAM and the data bus settles during that time. The ZX RAMPAGERv2 circuit shown fixes that problem by replacing U2 with my favourite decoder chip, the 74HC251 and adding RFSH enable decoding.
Here then is the new description of operation.
I recently harvested some 4Mbit SRAMs from some old hard drives for free. To squeeze these large memery chips into the ZX81 64K memory map 8-16K, I designed RAMPAGER2, a simple project to expand ZX81 memory by 512k bytes organized as 64 pages of 8K bytes each. I will describe the circuit using a HM62512 SRAM chip but a 29C040 Flash memory is also supported although it requires more complex software to handle the sector writes. Smaller memories such as the 62128 (16 pages) and 62256 ( 4 pages) can also be used with appropriate changes in the pin numbers.
ZX RAMPAGER2 is based on a similar bank switch project I designed (and still have) in 1986 using multiple 8K byte RAM chips all mapped to the 8K-16K area and another project I did (and still have) in the early 90s using two 128K byte memory chips mappped as 16 pages of 16K bytes located at 48K - 64K.
PAGED MEMORY (U4)
Most of the paged SRAM chip (U4) pins are directly connected to the ZX81 expansion bus including data pins D0-D7 and address pins A0-A12. The 1 of 64 page selection is controlled with SRAM pins A13-A18 connected the software programmable 8 bit Page Register chip (U3) outputs pins. The SRAM memory contents are made non-volatile with the simple battery backup circuit shown. The data contents of the paged memory are protected with a manual swich S1 or with a software controlled write protect bit also provided by the Page Register. It is recommended that write protect switch S1 is closed before powerdown and during normal use when no or read-only access to the paged RAM is anticipated. Output Y of U1, the Memory Address Decoder, is used to chip select the selected 8K page of SRAM U4 in the memory area located at 8-16K. The SRAM CS and OE pins are connected together to this chip select signal. This would normally generate data bus conflict during write cycles but this is avoided here since the Z80 data bus is internally isolated with resistors from the external data bus. This parallel select of CS and OE is the conventional method used for, example for the ZX81 RAMCS signal and most other memory expansion projects except those that use a buffered external data bus.
PAGE REGISTER (U3)
The Page Register chip U3 is a 74HC273 which is cleared by the RST signal to all zero on power up and reset. Six bits of the resister outputs (Q0-Q5) are connected to A13-A18 of memory chip U4) to select 1 of 64 pages of 8K bytes. Q6 is used to write protect the data contents of U4. Register bit Q7 is not used here but can be available as an auxilary output. The Page Register data is loaded by POKEing the page number to an even (write enabled) or odd (write protected) address between 4096 and 8191 for example:
POKE 8000, 0-63 - to select page 0-63 with write enabled or
POKE 8001, 0-63 - to select page 0-63 with write disabled
Bit 7 can be set high by adding 64 to the page number when poking the page number.
and is set low by poking the page number by itself.
PAGE REGISTER ADDRESS DECODER (U2)
Any write operation such as POKE to the 4K -8K area of memory is decoded by the Page Register Address Decoder 74HC138 chip (U2) which generates a low pulse on output Q1 when A13, A14, A15,MREQ and WR are low and A12 is high. This low pulse on U2/Q1 performs two furnctions:
1) Q1 is connected to the Memory Address Decoder (U2) input D0 which disables the ZXROM data lines while writing the page number to the Page Register.
2) Q1 is also connected to the Page Register clock pin and on the rising edge of the low pulse on Q1, the page value 0-63, write protect and AUX bits are clocked into the page register.
MEMORY ADDRESS DECODER (U1)
The Memory Address Decoder (U1) uses a 74HC251 chip. Outputs pins Y and /Y are normally tristate. A pull up resistor on Y holds the SRAM chip select normally high. The Y and /Y ouputs go active high or low when MREQ or RFSH is low. The logic level of Y and /Y depends on the state of 1 of 8 input pins of U2 (D0-D7). These inputs are all wired high except for D1 which is low or D0 which can be either. D0 is controlled by U2/Q1 and goes low when the Page Register is POKEd. The inputs are selected with A13,A14 and A15 corresponding to enabling 8 possible areas of 8K each in the 64K memory space of the Z80.
If desired, the location of the Paged Memory can be changed from 8K-16K to 32K-40K or 40K-48K. Alternatively, the page size can be expanded to 32 pages of 16K each located between 32K and 48K. Yet another variation provides 32 x 2 x 8K pages each of which splits a 16K page between 8K-16K and 32K-40K
The diode connected to the /Y output is used to disable the ROMCS signal to the ZXROM when writing to the 4K-8K area. The latter occurs when U1/Q1 places a low level on D0 which sends a high level through the diode to the ROMCS line when the 4K-8K area is POKED with the Page Register data. During access all other memory areas, the ROMCS line is not affected.
This 512K byte ZX RAMPAGER circuit expands the ZX81 memory by 512K bytes of non-volatile SRAM organized as 64 pages of 8K bytes. These pages can store any ZX81 software including MC programs or hires screens which can be quickly flipped for animation. A simple directory control program (RAMDOS1) can be adapted to select pages, to display a directory of the page contents and allow saving and loading of binary files, basic programs and basic variables to each page.
- v0.2 replaces U1 with a 74HC251
- (12.91 KiB) Downloaded 2880 times