First I added some logic for software Vsync control, but since that isn't (directly) used for any ULA output pin: how to test? Therefore decided to add a few counters & logic to decode a certain value range in those counters. One for horizontal, reset by Hsync & clocked by 3.25 MHz. And one for vertical, reset by Vsync & clocked by Hsync. Then a simple AND gate to produce a signal that basically should be '1' in a rectangular area (roughly upper left corner).
Next a gate to mix the sync signals into composite sync, and after a back-of-the-envelop calculation, hooked up a cinch connector using just 2 of the CPLD's I/O pins + 2 resistors. And guess what: an image!
Stable, bright white rectangle, crisp edges around it, with a deep black background. Still nowhere near a full ULA replacement, but this result is important because:- It shows that the software Vsync generation works.
- It shows that method for mixing the sync signals works & TV is able to lock onto both horizontal, and vertical sync.
- That crude video out using just 2 resistors works, producing correct voltage levels for sync, black & white.
- And I now have a nice 'channel' through which I can display signals (like what's picked up from databus etc).
To do:
- Line counter that goes 0..7, and output that at the right time to A0~A2 lines.
- Grab character code from databus @ the right time, and output that shortly after to some more address lines.
- Feed-NOP-to-Z80 circuitry.
- Grab graphics data output by the ROM @ yet again the right time.
- Shift those bits out serially (piece of cake when the rest is done).
- Some minor bits like keyboard inputs, inverted video etc.
It's all part of producing something you understand ! Again my 1st priority is get rid of original ULA - @ that point things should get easier.