Clock doubling on ZX80... is it possible ?

[Andy Rea]

So i was thinking is it possible to do clock doubling on a ZX80 (running in ZX81 hardware)....

from my limited look at the ZX80 it seems that when it's waiting for a keypress it runs a loop that does the vsync, scans the keys, branches out if a new key is pressed, otherwise displays the picture, and loops round again for another go...

So the idea is can i monitor the M1 cycles (complete with the execution address) and when it enters the loop disbale clock doubling, and then when it leaves the loop enable it again ?

This is just an idea so don't hold your breath.

Andy

[siggi]

Hin Andy,
there are some "flicker-free" ZX80 games available, which handle the display itself. So "watching" an address in ROM address space won't help ...

Siggi

[Andy Rea]

Hi,

Ah yes i never thought of that, So lets say for-going the flicker free programs.... would it work ?

Andy

[siggi]

As In understood, the ZX80 would run in "double-FAST-mode", always when it does not display a picture.
But then other "real time" routines would also run too fast: tape LOAD/SAVE

So you have to watch also their address ...

Siggi

[Andy Rea]

Hmm goog point, i'll put this problem to one side for a bit, till after i perfect ZX81 operation....

Andy

[PokeMon]

Andy,
if you plan a clock generator for the ULA, you should test with a 6,75 MHz clock instead of a 6,5 MHz clock (another crystal).
The reason is, as international PAL TV standard sampling frequency was defined with 13,5 MHz.
The result is a better quality picture on TV's and frame grabbers because with this freqency, every ZX81 pixel is exactly on a TV pixel, so no interpolation.

see here
http://en.wikipedia.org/wiki/PAL

But if you do (running higher frequency) you have to adapt h-sync and v-sync counters. But in your own ULA you could do.
This was a proposal from me in the german forum but I think TV's could have problems because this will result in 62,5 us line duration / 16.225 Hz horizontal frequency resp. 52 frames per second. And ZX81 would be 3% faster. But main reason is the supposed better picture quality.

[PokeMon]

And one more idea, what about using a 6 MHz version of Z80 cpu and no clock halfing ?
Maybe you have to enter 4 wait states in that nop session but this could double Zeddy performance significantly.
As datasheet it can be clocked up to 7,7 MHz (65 ns per clock high/low), so this would work with proposal no.1 for 6,75 MHz for better video signal quality and give this clock rate to cpu.

Another idea could be to use double screen resolution (64 chars / line) with a small rom modification and to use no wait states, just two nop's.
And 48 display lines instead of 24. But this has to work with real interlaced video signal, so displaying line 1,3,5,7 in first frame and line 2,4,6,8, in second frame.
More work for the ULA but maybe also more fun for us when it works.

Just an idea but I would keep in mind the proposal with 6,75 MHz clock, see post above.

[Andy Rea]

Hmmm, quite interesting that Wiki... but...

it seems that the 13.5Mhz you refer to is for digital sources, which probably explains why whenever i have connected the PC to a standard PAL tv the results are less than perfect...

I also note that the Maximum video bandwith for any PAL system (J/K) is 6Mhz therefor the ZX80 / 81 video at 6.5Mhz is outside of this parameter...

However When used on a monochrome monitor, I.E. no colour mask inside the tube, Then the clarity and sharpness is really very good.

currently as it stands, i have no plans to move the crystal from the mainboard onto the ULA, so for now we are stuck at 6.5Mhz

Andy

[Andy Rea]

64 chars per line and true interlaced display.... we are really getting out of ordinary TV world now...

64, 8 bit wide chars would be un-readable on a normal TV

Andy

[zx80nut]

The PAL "bandwidth" was exceeded my a few systems (notably the BBC Micro) which gave a very readable 80 character display on a normal TV set if the tuning was adjusted carefully, so no problem whatsoever in getting 64 chars per line.
So, don't worry about the bandwidth - that myth was dispelled back in 1982 by Acorn

I also do 80 char generation on a normal PAL timed signal (using an Atmel ATMEGA processor) here... http://home.micros.users.btopenworld.com/cpm/index.htm

I think 64 chars (permanent clock doubling) may need the following changes...
1. The ROM needs changing (yeah, obvious) to set the appropriate values for "int" triggering at the end of each line, VSYNC delayed longer etc.
2. The HSYNC would be too short - extra circuitry would be needed to stretch it. ZX81 uses 16 clock cycles, the ZX80 uses a couple of M1's

The A6 line going low that triggers an int may need a bit of thought, just in case it occurs twice during the scanline when using a 6.5MHz CPU clock.

Grant.