ULA revistited.

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Prime
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Re: ULA revistited.

Post by Prime »

sirmorris wrote:I wanna play!

Maybe not with the ULA board but certainly with some kind of dev kit.
I always find after a very short time the extra hardware on a dev board gets in the way :(

Do you have some breadboard ? If so I could make you a PLCC to breadboard adapter, I prolly already have the board made would just need to drill and mount headers / socket.

You'd also need a paralell port programmer, but you can make that up with a single LS chip and a couple of descretes.

Failing that I could lend you my Diligent Xilinx dev board which has an XC9772XL and a Coolrunner on it.

Cheers.

Phill.
sirmorris
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Re: ULA revistited.

Post by sirmorris »

I have a 44pin breakout.

And I made one of your jtag boards - never used it but I made it :)
Prime
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Re: ULA revistited.

Post by Prime »

I think I have the clock doubling working, though it does seem a little glitchy when enabling / disabling when running, but that could be cause I'm just using a push switch as a test in reality it would be enabled at reset (or possibly by an out instruction) and then left enabled. Seems stable enough when it's running.

One thing I did notice, the machine runs fine clock doubled running off the faster RAM on the ZXpand, but falls over with the onboard 2K RAM (6116-4), which I suspect is down to the RAM being too slow :(

I'll post the code later when I've tested it some more.

Cheers.

Phill.
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Andy Rea
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Re: ULA revistited.

Post by Andy Rea »

Thats good news, i have 80ns memory chip in my Zeddy, even at 6.5Mhz the shortest memory read is 2 cycles, that approx 308ns @ 6.5Mhz surely the onboard ram is not that slow ?

there are times you would want to switch the turbo mode off, for example when entering programs, when the new line is entered the video system does a restart ( i presume because D-file has moved) and it tests for the presense of an NMI generator, if turbo is enabled it (mosy of the time) thinks there is no NMI generator and goes into fast mode.

i too have clock doubling working, using code based on that i used in the GAl, it does not suffer with the display corruption that the gal did, so it was either stray capacitance or clock skew causing it.

this is code for manually controlled turbo off a toggle switch, switch high = enable.

Code: Select all

wire slow_clock;
wire fast_clock;

/* clock doubling based on this wincupl code


		
addhigh = a7 & a6 & a5 & a4 & a3 & a2 ;

clkout = (!turbo & slowclk) # (turbo & fastclk);
turbset = (turboon & iorq & wr & addhigh & a1 & !a0 & !halt);

turbunset = !turboon # halt # (iorq & wr & addhigh & a1 & a0) 
			# (iorq & wr & addhigh & !a1 & a0);
 
turbo.d = (turbset) # (turbo & !turbunset) ;

*/
 
wire addhigh;
wire clkout;
wire turbset;
wire turbunset;
reg turbo_active;

assign addhigh = add_low[7] & add_low[6] & add_low[5] & add_low[4] & add_low[3] & add_low[2] ;

assign fast_clock = osc;

assign clock_out = (!turbo_active & slow_clock) | (turbo_active & fast_clock);

assign turbset = (turbo_enable & !iorq & !write & addhigh & add_low[1] & !add_low[0] & halt);

assign turbunset = !turbo_enable | !halt | (!iorq & !write & addhigh & add_low[1] & add_low[0]) 
					| (!iorq & !write & addhigh & !add_low[1] & add_low[0]);

assign turbo_act = turbo_active;

always @ (posedge slow_clock) begin

	turbo_active = (turbset) | (turbo_active & !turbunset) ;
 end
Also if glitch free switching you should be able to switch between turbo and non turbo whenever you like, i'll post some simple video later.

regards Andy
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Andy Rea
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Re: ULA revistited.

Post by Andy Rea »

little video showing Clock doubling at work...

http://www.youtube.com/watch?v=2sFSdBGc09I

Andy
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Prime
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Re: ULA revistited.

Post by Prime »

Andy Rea wrote:Thats good news, i have 80ns memory chip in my Zeddy, even at 6.5Mhz the shortest memory read is 2 cycles, that approx 308ns @ 6.5Mhz surely the onboard ram is not that slow ?
Checked the datasheet it's 200ns, which by your calculations sould be ok.

On further investigation, it works fine with Charlie's ZXpand plugged in but doesn't work on the internal RAM, I don't think speed is an issue as my other experemental machine has a 32K 20ns SRAM in :) So I guess the problem must have to do with how the internal /RAMCS is implemented by the CPLD code, will investigate. Wonder if it's worth trying with my Memotech RAM pack.
there are times you would want to switch the turbo mode off, for example when entering programs, when the new line is entered the video system does a restart ( i presume because D-file has moved) and it tests for the presense of an NMI generator, if turbo is enabled it (mosy of the time) thinks there is no NMI generator and goes into fast mode.
Yeah I found that out by accident, fortunatly I have the switching working now without glitching so once I get the /RAMCS issue sorted I should be good to go.
i too have clock doubling working, using code based on that i used in the GAl, it does not suffer with the display corruption that the gal did, so it was either stray capacitance or clock skew causing it.

Also if glitch free switching you should be able to switch between turbo and non turbo whenever you like, i'll post some simple video later.
Yeah no video probs here either so looks like it was a problem with your GAL board.

I have to say your turbo demo program was much more visually impressive than mine :) I just did

Code: Select all

10 for a=0 to 1000 
20 print at 0,0;a;
30 next a
But then I was having to re-type every time so wanted it as short as pos :)

Cheers.

Phill.
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Andy Rea
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Re: ULA revistited.

Post by Andy Rea »

Prime wrote:
Andy Rea wrote: Oh and this is ULA-Plus were talking :D

i seem to have sorted it now, as i have re-written that bit and it once again seems to work fine.
Andy since you have a ZXpand now, can I ask you to test something for me ? I've only been able to get the clock doubling working with ZXpand fitted and the external ROM enabled. If I unplug ZXpand or dor a CONFIG "X" to disable it's clock, then the machine crashes as soon as I enable the clock doubling, does this affect your current design.

How are you implementing /ROMCS & /RAMCS in your ULAplus now that you have it all in the CPLD ?

Feel free to reply in the ULA thread if you feel it would be more apropreate there....

Cheers.

Phill.
right where to start, with the easy bit i guess, RamCS and RomCS is as on standard ULA

Code: Select all

assign romcs = a14 | mreq ;
assign ramcs = !a14 | mreq ;
for the extra features, they are all coded to be off by default, so on power-up or reset ;) ( wired to pin26 of the cpu...) the zeddy powers up as normal, the only way of enabling features then is by doing an ' OUT A,($7F) ' where as bits 4 - 0 control the various features, the row of keys are scanned at startup and stored so on power-up/reset 'b' is bit 4, spc is bit 0

bit 4 = turbo_enable (extras[4] in the code '1' = inactice, 0 = active
(but it is still manually controlled by an external switch) the switch is ignored if turbo_enable is '1'
bit 3 = M1not_enable '1' = inactive, 0 = active
when active video cycles only occur in the upper 16K (a14 needs to be high in addirtion to a15) , i'm not actually altering the M1 signal at all !
bit 2 = invert uk/us mode , '1' do not invert, '0' invert
bit 1 = invert video, '1'= normal, '0' = inverted (white on black
bit 0 = invert Border '1' = normal, '0' = inverted (black)

Then we move onto clock dopubling....

Code: Select all

wire slow_clock;
wire fast_clock;
input turbo_enable;
wire addhigh;
wire turbset;
wire turbunset;
reg turbo_active;

assign addhigh = add_low[7] & add_low[6] & add_low[5] & add_low[4] & add_low[3] & add_low[2] ;

assign fast_clock = osc;

assign clock_out = (!turbo_active & slow_clock) | (turbo_active & fast_clock);

assign turbset = ((turbo_enable & !extras[4]) & !iorq & !write & addhigh & add_low[1] & !add_low[0] & halt);

assign turbunset = !turbo_enable | !halt | (!iorq & !write & addhigh & add_low[1] & add_low[0]) 
					| (!iorq & !write & addhigh & !add_low[1] & add_low[0]);

assign turbo_act = turbo_active;

always @ (posedge slow_clock) begin

	turbo_active = (turbset) | (turbo_active & !turbunset) ;
 end
almost the same s before.... just the addition of extras[4], which if high turboset can never be asserted.

i don't appear to have any problems with switching between turbo and non turbo whilst programs are running, up until the M1not issue i was having it worked fine with or without ZXpand plugged in, but i have ripped out the interanl ram for the moment, i can however issue a CONFIG "X" whilst clock doubling is active, and can perform for example LOAD "25THANNI;X" whilst clock doubling is active all fine, alothought the only part of 25thanni that benefits is the second part, the rest seem to be tied to the frame rate.

If i haven't exactly answered what you were asking feel free to ask again :lol: sometimes i miss things.

Regards Andy
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Andy Rea
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Re: ULA revistited.

Post by Andy Rea »

Another Video on youtube http://www.youtube.com/watch?v=V0BzFBIwDV8

Decided i better have a root around the box of junk because i knew i had a video capture card somewhere :D but it does not like 60Hz video at all so i did not demostrate that.

So extra features can be altered by program (only M/C as it's on a port, not memory mapped) or can be selected at power-up or reset by holding down various keys along the row 'B N M . spc'

the reset signal is a bit of a cheat because original idea was to only connect to Zeddy board via 40 pins of the ula socket, but now 1 external connection is required, but it works fine without, except if you can't do M/C to alter features you must power cycle.

Regards Andy

P.s. for Prime, i noticed sometyhing pretty neat with the M1not and turbo combination if running in turbo mode, and you try to excute code in the 32-48K region it will execute even when M1not is not enabled, this is because... i am testing for a valid video cycle 1/4 of a 3.5Mhz clock away from the rising edge of T3 (when the CPU needs to see a nop, during a normal video cycle) but and heres why it does it. when the cpu is running at 6.5Mhz the rising edeg of T3 has been and gone while the ULA is still testing for a valid video cycle during the refresh cycle, M1 has gone high already so no video cycle happens.

i have yet to confirm this behaviour on a real ULA but will do so shortly.

Andy
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Andy Rea
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Re: ULA revistited.

Post by Andy Rea »

After Many weeks waiting frustrated for the Altera programmer to turn up from china, it finally arrived yesterday :D So i knocked up an adapter with some flying leads to solder to the PCB pads.

Image

To my imense relief it works :lol: i was a little worried that i could of wasted a few quid getting PCB's made before even prototyping with the Altera chip.

although it is a 3.3v device it runs quite cool, there was some speculation that driving over 1/2 of the i/os with 5v signals could cause some heating even thought they are rated TTL compatible. So thats another relief.

Image
Image
Image

to get the second screen to appear as it does rather than a set of vertically alligned bars proved a little tricky, it's all about when the Hsync/nmi Gen counter is actually reset, it turn out that it's a bit of a throwback from the zx80 design, the hsync counter is NOT reset by Vsync but by an INT acknowledge, the hsync occurs 16 (3.5Mhz) clock cycles later. where as when running in slow mode the NMI and Hsync occur together.

and just because i like pictures :D

Image

regards Andy
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Re: ULA revistited.

Post by Andy Rea »

I'm slowly getting there, after the initial high hope, the 'little green board' was proving a bit troublesome, i could load a demo and literattly leave it running for hours without a problem, the trouble started when i was manually entering programs, it would crash frequently for no apparent reason, first i looked at the forced/nop read port $FE part of the design (they share access to the data_bus) wrote about 7 different versions and all exhibited the same un-solved behaviour, i then moved on to play with the video cycle routine, because i noticed that sometimes instead of crashing i would get some interference on the display (only for 1 video frame) but alas no joy there either, So i decide i'm going to completly re-write it from the ground up...

and well the rewrite doesn't work either (yet) but the older version does :D during testing / simulation of the re-written version instead of a state-machine orchestrating the video cycles i decided to try things differently and sequencialy trigger flip-flops all on various clock edges...

it was during this part of the simulation that i found that really long M1 cycle ( the INT acknowledge) was throwing things all out of whack. so instead of just testing D6, M1, HALT, A15, i am also testing the RD signal as this is a sure way of telling if it really is a M1 op-code read cycle.

anyway the re-written version has gone on hold for the moment. and i quickly threw in the RD test into the old version and bingo, so far so good.

regards Andy
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