The version 1.71.01m.Z80 of ZX-IDE supports now all undocumented opcodes/instructions as they have been researched and published from Sean Young. The latest version 0.91 can be downloaded here:
http://www.myquest.nl/z80undocumented/
Previous versions allowed only the official instructions published from ZILOG. The IDE supports now some new features with read of .p files and disassembling as well and many programs did use undocumented opcodes in the past. So I decided to support all undocumented instructions as well to let the source to be recompiled after maybe some changes.
Mainly the undocumented instructions refer to the lower und higher 8 bit parts of IX and IY in the same way H and L can be used as 8 bit register or 16 bit register HL. As planned from ZILOG IX and IY can and should be used as 16 bit registers only but the decoding logic does allow the use as 8 bit registers as well. The usual naming for the registers are IXH and IXL or IYh and IYl. For these kind of symbols (not labels !) and instructions the ZX-IDE does not distinct between upper and lower case. So IxH and iYl are possible namings as well. Additional a new SHIFT instruction und some new special BIT and rotate instructions are supported. I will come back later to this.
Code: Select all
0097: [40A0] DD 7C LD A,IXh
0099: [40A2] DD 7D LD A,IXl
009B: [40A4] FD 7C LD A,IYH
009D: [40A6] FD 7D LD A,IYL
009F: [40A8] 67 LD H,A
00A0: [40A9] DD 67 LD IXH,A
00A2: [40AB] DD 60 LD IXH,B
00A4: [40AD] DD 61 LD IXH,C
00A6: [40AF] DD 62 LD IXH,D
00A8: [40B1] DD 63 LD IXH,E
00AA: [40B3] DD 64 LD IXH,IXH
00AC: [40B5] 65 LD H,L
00AD: [40B6] DD 65 LD IXH,IXL
00AF: [40B8] DD 6C LD IXL,IXH
00B1: [40BA] DD 6D LD IXL,IXL
00B3: [40BC] FD 64 LD IYH,IYH
00B5: [40BE] FD 65 LD IYH,IYL
00B7: [40C0] FD 6C LD IYL,IYH
00B9: [40C2] FD 6D LD IYL,IYL
You can see easily the substitution of registers H and L for IXh, IXl, IYh, IYl while adding the prefix DD or FD to the instruction byte. LD H,A equates opcode $67 and LD IXH,A correlate to $DD,$67. Additional to all load instructions all arithmetical and logical instructions can be used as well in all cases, where H and L are supported:
Code: Select all
00C1: [40CA] DD 8C ADC A,IXh
00C3: [40CC] DD 85 ADD A,IXl
00C5: [40CE] FD A4 AND IYh
00C7: [40D0] FD BD CP IYL
00C9: [40D2] DD 25 DEC IXh
00CB: [40D4] DD 2C INC IXl
00CD: [40D6] FD B4 OR IYH
00CF: [40D8] FD 9D SBC A,IYL
00D1: [40DA] DD 94 SUB IXh
00D3: [40DC] FD AD XOR IYl
Interesting is the use of IX and IY with displacements and a second register for all bit instructions (SET/RES), shift instructions (SLA,SRA,SRL) and rotation instructions (RL,RLC,RR,RRC). These instructions stores the result in the memory addressed operand (IX+/-n) as well as in one of the 8 bit register A-L. Uncommon is the "dual" notation with a second register.
Code: Select all
00DB: [40E4] DD CB 03 86 RES 0,(IX+3)
00DF: [40E8] DD CB FD 87 RES 0,(IX-3),A
00E3: [40EC] DD CB FD 80 RES 0,(IX-3),B
00E7: [40F0] DD CB FD 81 RES 0,(IX-3),C
00EB: [40F4] DD CB FD 82 RES 0,(IX-3),D
00EF: [40F8] DD CB FD 83 RES 0,(IX-3),E
00F3: [40FC] DD CB FD 84 RES 0,(IX-3),H
00F7: [4100] DD CB FD 85 RES 0,(IX-3),L
00FB: [4104] DD CB 7F C0 SET 0,(IX+$7F),B
00FF: [4108] FD CB 80 C7 SET 0,(IY-128),A
0103: [410C] DD CB FF 17 RL (IX-1),A
0107: [4110] FD CB 02 10 RL (IY+2),B
010B: [4114] FD CB 00 01 RLC (IY+0),C
010F: [4118] DD CB 40 1D RR (IX+40h),L
0113: [411C] FD CB 0F 0F RRC (IY+0Fh),A
0117: [4120] FD CB FE 21 SLA (IY-2),C
011B: [4124] DD CB 11 2B SRA (IX+17),E
011F: [4128] FD CB F8 38 SRL (IY-8h),B
The first RES instruction is the standard use case and stores the result in IX+3. All following instructions do the same (with a different offset) but with a second 8 bit register as well. The result will be stored in both places, the memory and the 8 bit register as a copy of the result. This allows store and easy and fast additional operations. If IX or IY is addressing memory in ROM area, the result is stored in the 8 bit register only as the ROM can not be written to.
There is additional a new shift instruction available, SLL or shift logical left. This is like SLA (shift arithmetic left) but put a 1 in the lowest bit instead of 0 like SLA. The new instruction can be used for all typical registers and memory referencing.
Code: Select all
0129: [4132] CB 37 SLL A
012B: [4134] CB 30 SLL B
012D: [4136] CB 31 SLL C
012F: [4138] CB 32 SLL D
0131: [413A] CB 33 SLL E
0133: [413C] CB 34 SLL H
0135: [413E] CB 35 SLL L
0137: [4140] CB 36 SLL (HL)
0139: [4142] DD CB FC 36 SLL (IX-4)
013D: [4146] FD CB 08 36 SLL (IY+8)
0141: [414A] DD CB 01 37 SLL (IX+1),A
0145: [414E] DD CB 01 30 SLL (IX+1),B
0149: [4152] DD CB 01 31 SLL (IX+1),C
014D: [4156] FD CB 01 32 SLL (IY+1),D
0151: [415A] DD CB 01 33 SLL (IX+1),E
0155: [415E] DD CB 01 34 SLL (IX+1),H
0159: [4162] DD CB 01 35 SLL (IX+1),L
There are 2 new I/O instructions. IN F,(C) reads data from port (C) but does not store the value but sets all flags like all other I/O instructions depending on the read data. This is the reason to use the acronym IN F,(C). So the flags can be set/tested without destroying any registers contents. There is a second interesting I/O instruction, OUT (C),0 which puts out a zero byte ($00) to the port addressed by register C. This saves the other 8 bit register contents as well.
Code: Select all
0163: [416C] ED 78 IN A,(C)
0165: [416E] ED 70 IN F,(C)
0167: [4170] ED 79 OUT (C),A
0169: [4172] ED 71 OUT (C),0
Flags changed with any IN instruction:
S is set if input data is negative; reset otherwise
Z is set if input data is zero; reset otherwise
H is reset
P/V is set if parity is even; reset otherwise
N is reset
C is not affected
Finally there are 2 control directives to allow or denie the undocumented instructions during assembling. Z80LOOSE allows the additional instructions while Z80STRICT will throw an error message when these instructions are used. Default at start of assembly is Z80LOOSE. These control directives can be used many times during assembly to allow or restrict these instructions for different assembly parts.
Code: Select all
Z80strict
0171: [417A] CE 63 ADC A,99
0173: [417C] 8F ADC A,A
0174: [417D] 8E ADC A,(HL)
0175: [417E] DD 8E 01 ADC A,(IX+1)
0178: [4181] FD 8E FF ADC A,(IY-1)
Z80loose
017B: [4184] DD 8C ADC A,IXh
017D: [4186] DD 8D ADC A,IXl
017F: [4188] FD 8C ADC A,IYh
0181: [418A] FD 8D ADC A,IYL