ZX81 ULA-in-a-CPLD

[Andy Rea]

My ULA was also tortured and I did a few minor mods earlier today. Now Zeddy boots up every time to the 'K' prompt. Screen and border inversion works as it should. Anyway, still works in progress.

Good stuff indeed, keep at it and you'll soon be a zeddy master

[McKlaud]

Yeah! Master of Disaster

[mrtinb]

Anyone implementing option to switch between normal black on white and inverse white on black?

[McKlaud]

Yes. See below

[1024MAK]

Nice

Mark

[McKlaud]

I am back to square one. No proper keyboard reads, my Zeddy boots to the "K" prompt in the FAST mode only, a lot of noise on the ground plane of the Zeddy PCB and the noise is visible in the video signal too.

[Andy Rea]

I am back to square one. No proper keyboard reads, my Zeddy boots to the "K" prompt in the FAST mode only, a lot of noise on the ground plane of the Zeddy PCB and the noise is visible in the video signal too.

Oopsy, I'm sure you will fix it. And yes the noise in the video is rather annoying.

Andy

[McKlaud]

It seems that I am back on the track. The ULA is alive, works in FAST mode only, loads some BASIC software, reads keyboard, execute BASIC command. Furthermore I ran a BASIC benchmark and its execution time was the same like my other Zeddy in the FAST mode.

Regarding "SLOW" mode, see the screen shoot shown below.

I've also noticed that sometime I can see a flash of a colourful (mainly pink-ish) pattern on the screen, mainly during boot up sequence. It happens randomly and it is just a flash and after that everything is back to normal. It is impossible to capture it in the photo or by oscilloscope, because it can be seen for less than second.

[Andy Rea]

Well i have had a positive day, drawing timing diagrams and then working out timings based on actual chip specifications, i have also reduced the switching noise during a forced nop somewhat..

the old way the force nop started at the middle ( falling edge ) of T2 however my new way, the RAMcs get de-asserted at this time but the forced nop does not start until another 1/4 cycle ( or half a 6.5mhz cycle ) The Zilog Z80a needs a 35na setup time before the rising edge of T3 when the data bus is sampled, we have about 79-35 = 44ns for the CPLD to pull the lines low and stabilize. i have tested this new approach with zilog 1984 vintage CPU ( probably nmos i guess, a nire modern 2005 vintage zilog Cmos variety, an SGS thimson Z80a of unknown but guessing 80's and finally an NEC D780C of 1982 vintage, all appear to work fine with this forced nop scheme.

Regards Andy

[siggi]

the old way the force nop started at the middle ( falling edge ) of T2 however my new way, the RAMcs get de-asserted at this time but the forced nop does not start until another 1/4 cycle ( or half a 6.5mhz cycle ) The Zilog Z80a needs a 35na setup time before the rising edge of T3 when the data bus is sampled, we have about 79-35 = 44ns for the CPLD to pull the lines low and stabilize.

Hi Andy
did you also test that with additional capacitive load on the databus?
My Zeddies can drive up to 4 external cards (I/O mapped) at a small backplane connected to the edge connector. That works fine, only the /clock-signal is arriving bad at some external boards.

Siggi

PS: Maybe some complex external cards, which "listen" on the bus to the Z80 actions (like Chroma81 or ZxBlast) could also get confused by a new timing ...

PS/2: and some "switching noise" is not bad. So I can hear in the radio, that my web server is still running