ZXmore or the ZX80CORE follow-up

[PokeMon]

Try the following setup (remove carefully all chips from sockets like in the picture during power-off).
This way you can measure quite a lot. The picture won't be displayed well but that is not important now.

IMG_9047k.JPG (72.13 KiB) Viewed 3770 times

Begin to measure the CPU.
First the address bus.
This should show on A15 a signal which is 20ms low and 20ms toggling between high and low.
Then goto A14, this should have double frequency (10ms low and 10ms toggling).
Then goto A13-A0 while the frequency doubles every time.

This setup let the CPU read regular NOP instructions which gives a counter on the address bus.
When you measures A0 (you should increase the horizontal solution / timing on your scope) go ahead with other signals:

D0-D7 must be zero - always low.
INT is the same as A6 as this is hardwired in the ZX81.
NMI, HALT, IORQ, WR, BUSAK, WAIT, BUSRQ, RESET must be high (no pulse).
MREQ should toggle with a longer and a short pulse, repeating every 600 nanoseconds.
RD,M1,RFSH should give a low pulse every 600 nanoseconds as well.

Please report.

[Lurch666]

EDIT:did this before I saw your latest post.Will try the new suggestions and report back tomorrow.(Shouldn't have started drinking while doing this.My results might be affected by alcohol now)


OK.No shorts that I could find but I have found out that sometimes when I power up the ZXmore I don't get signals.
After messing around I have managed to find out I was getting signals from some of the pins I thought stuck high.Just had to find the correct settings and make sure I was getting signals in the first place.

Anyway the scope does have two probes so I was able to check out some of your suggestions and try some signals side by side.

Pins 6 and 28 (To make sure the clock wasn't something to do with the scope) pin 6 on the bottom:




Pins 21 and 22.Pin 21 on the top:



and lastly pins 27 and 28.27 on top.

[PokeMon]

If this works and you think the signals are showing correct, go ahead with following signals:

RAM, pin 22 (CE) should be high for 10ms and toggling for 30ms.
ROM, pin 22 (CE) is toggling always but on my scope I see a difference in the high level during the 10ms (bit different from the 30ms)

This is because ROM is addressed from 0-16383 (25% of address room) and RAM is addressed from 16384-65535 (75% of address rom).
The ROM is additionally activated during refresh while the index register is zero and addresses ROM only.
The OE pin of RAM and ROM (pin 24) should show a pattern with two low pulses directly after each other in a 600 nanosecond repetition which may seen as a short and a very short high pulse. The very short may not be seen good on your scope depending on it's resolution. This is more a glitch of about 10 nanoseconds.

The address lines A16, A17, A18 should be high (voltage lower than 5V but above 2V anyway). This is for the ROM only and changes when setting switch / showing LED colour. There shouldn't be any pulse here. The RAM higher address lines are controlled via a register which is not present now.

Additionally check the clock signal at pin 12 of IC12 (6.5 MHz) and pin 12 of IC9 (3.25 MHz).
Now check the horizontal frequency at pin 4 IC6 - should be a low pulse about 5.5us width, repeating every 64us.
Finally, IC5 (which is not present now, so measure its socket pins) - pin 19 must be low (DBDIR) and pin 1 must be high (WR).
That's it for the moment.

[PokeMon]

Okay - regarding you last posting - did you remove the ICs as shown on the picture ?
This is wrong as there are /WR pulses.
RFSH and M1 are toggling only - when M1 goes low, RFSH goes high and vice versa and every period is exactly 2 clock cycles. So 2 clock cycles M1 low followed by 2 clock cycles RFSH low, repeating all time.

Can you measure the database at the CPU ?
All pins must be low.
Important is that chips are removes as seen on the picture I posted.

And yes - maybe continue tomorrow. Too much beer doesn't help finding errors in my experience - mostly does the opposite.

[Lurch666]

I didn't remove the chips when doing those last tests.
Will continue tomorrow when the beer has worn off.

[Lurch666]

OK chips removed and tests done.

Most have returned the correct results but there are a few possible problems.I don't know if it's me getting the settings/calibration wrong with the scope or if it's an actual problem with the ZXmore.

A15-A7 work as expected with each successive one being half the size of the last and toggling correctly.A6-A0 don't seem to toggle between low and high.

A7:



A6:going high and staying there:



Pin 19/MRQG:seems to work as stated but is the frequency correct?



the frequency of RD,M1,RFSH seems too low as well

Pin 27/M1:



Pin20/RD:



RFSH was the same.If these are supposed to have a frequency of 600ns this looks wrong.

Pin 12 of IC12 looks correct but I don't know how to work out it's frequency in Mhz.



Pin 12 of IC9 was the same signal but twice as wide which is correct for half the frequency if I'm understanding it correct.

Everything else appeared correct.

[PokeMon]

These signals are looking correctly.
All are in a 600 ns window (while having 6.5 MHz clock with 4 clock cycles) - you have 200 ns per div and 3 divisions per period of a signal. Also MREQ is correct as this is active two times in one period, one longer during M1 and one shorter during RFSH.

Can you proof the second part of my message as well with measuring ROMCS, RAMCS and the horizontal sync and A16-A18 at the ROM ?

[Lurch666]

Yep I did all the tests in all of your posts.The only ones that didn't look right are the ones that I posted pictures of in my last post.
But what do you mean my ROMCS and RAMCS?
I did the horizontal sync,CE and OE outputs and A16-A18 and got the correct results.

[PokeMon]

Yes CE (chip enable) is the same as CS (chip select) and meant in conjunction with corresponding ROM or RAM.

Okay - the next step:
Add two 74HCT245 as shown in the picture.

IMG_9048k.JPG (94.29 KiB) Viewed 3641 times

This way you should get a valid video signal (if ROM and RAM are working correct).
There are only black chars displayed, this is not important.
It should not be a readable picture but shown a steady picture with some black bricks on the screen.
Each brick mark an inverted char or when choosing the ASCII charset a printable char.

There are also some more signals to measure now.
There also appear probably some moving pixels as there is an open pin (video polarity) but this is also not important.
It should be a synced picture. A reset should give the clean screen for a moment back.

A15 could be measured with 2ms per division and should show a package of about 12ms fast toggling (seen as a "package") followed by 3.5ms silence, a very short package and again 3.5ms silence and then repeating. This is a frame showing the picture generation (12ms = 192*64us), bottom margin (3.5ms = 55*64us), vertical sync action (what is seen here is the keyboard routine with A15 set), the second top margin (3.5ms = 55*64us) again.

When you take a higher resolution you can see the horizontal lines:
In 5us/div you should see 33 high pulses (40us), this is 32 chars plus the newline at the end, and then a pause of about 20us (maybe only 10us seen in this resolution).

Pin 17 of CPU (NMI) should show (with 2ms/div) 2 small low pluses, 4ms pause high, 2 additional small pulses and 16ms pause. This is the bottom and top margin begin. Pin 18 (HALT) should be seen as 4ms high, a long package of 12ms pulses (193x) and again 4ms high. Pin 19 of IC5 should show 12ms pulses and 8ms pause (low).

Well - will see what you find. All signals you measured till now seem to be correct. If the ROM is working correct the signals above should appear. And a kind of picture.

[Lurch666]

I must have messed up somewhere as I'm not getting a steady picture.It's rolling and its just a mess of broken black lines:



Although the black bar at the bottom is steady.
I'll remove those two chips again then go back and re-check the rom and ram.