commie wrote:Can I just make it clear, everything works perfectly, the picture is rock steady there are no glitches or hic ups on the screen, all the scope waveform's look good no glitches. In fact, it's working so good (..)
Well done commie! When screen output etc is all working, you're 99% there. Also gives
me a warm fuzzy feeling in my belly...
However, does anyone know what the differences are between fast and slow modes?, I know that the nmi is used in slow mode, what changes take place in the zx81's hardware/software?.
Like PokeMon said, in slow mode the NMI generator is turned on/off under software control (a few times per frame iirc). ZX80 doesn't support that as the NMI generator is missing. And with NMI generator disabled, ZX81 is basically a ZX80 with newer ROM.
I've implemented the zx81 ula in an Atmel ATF1504 (plcc44) cpld and its working great except for one feature, that is it doesn't work in slow mode only fast mode with the nmi pin strapped high. When I connect the nmi I get garbage on the screen, but the nmi pulses are active as seen on my scope.
When you get garbage on screen, does machine keep running? For example, can you still type things and see keywords etc appear on screen? Or maybe execute commands/previously entered program? Or garbage on screen as in "machine stops responding"?
With NMI's being generated, there's 2 things to check:
* Whether NMI generation can be turned on & off under software control (or you have NMI's always which wouldn't be right)
* At what point in time
exactly those NMI's are generated. The Z80 responds to NMI's at certain point(s) during processing instructions. If (for example) the NMI arrives 1/2 clock cycle too early or too late, that might be the problem.
If you are wondering how I sqeezed it all in plcc44, well the oscillator and flip flop(3.25MHz) are external and drive only the z80 whilst 6.5MHz osc. is fed into the cpld where the 3.25MHz and /3.25MHz are derived in the cpld.
Aiiii... so you may have timing differences between 3.25 MHz clock edges inside the CPLD, and clock edges the Z80 sees? That
might be bad.
![Mad :x](./images/smilies/icon_mad.gif)
Or not.
![Question :?:](./images/smilies/icon_question.gif)
Dunno. In my CPLD design I put both 3.25 MHz signals on global clock pins of the CPLD, meaning flip-flops clocked by the same clock edge are clocked with minimal time difference. No chance that a slightly early update of one flip-flop causes another flip-flop to be clocked with the wrong data. With 'next round of updates' a 1/2 clock cycle down the line...
I have read Retrotechie design report and it seems perhaps( I could be wrong) the design is incomplete (..)
Nah... that disable-NMI's-as-if-on-a-ZX80 feature looked too simple at the time. And I hadn't tested
that with a ZX80 ROM. Therefore wasn't 100% sure
that feature was complete/working as intended. And stated such in the docs.
With NMI generator enabled as on a ZX81, things are 100% working and I was
unable to find any software that worked different than on a ZX81 with Sinclair ULA. Timing-sensitive demo's, stuff that writes in the border area etc included. Doesn't mean my CPLD design behaves exactly like a Sinclair ULA! But
does mean the software/on screen effect is the same.