Announce: ZX80/81 NMI Generator V4

[Andy Rea]

normally we expect intack to occur on the 206 cycle of each scanline it lasts for 2 cycles and when released the count starts at zero again, the same as when the counter rolls over.... however you can write different display routines that can alter the timing of the scanline so if intack didn't occur until cycle 207 (AZMIC) and it still lasts 2 cycle we get 2 cycles where the output of the counter is zero...

this can be extended even further up until the hsync occurs, so we could in theory delay the hsync for 17 cycles by having intack occur at cycle 15.

what i'm saying is that the hsync happens 16 cycles after intack is released, if you engineer your display routine in such a way you can have scnline times shorter or longer than the 207 we all expect.

[PokeMon]

Anyway crazy stuff. Have to go deeper into it but atually didn't want to.

[RetroTechie]

Interrupt acknowledge (/M1 and /IORQ both active) occurs when the Z80 accepts a maskable interrupt (from /INT pin).

Remember that in ZX80 and ZX81, /INT pin is tied to A6. So depending on video code (and where in memory that code is!), programmers have some control over when /INT gets activated. And thus control over when the 207-cycle counter is reset. And thus some control over when the next hsync occurs.

Too tired right now to think about what programmers can & can't do to hsync's...