Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

General Chit Chat about Sinclair Computers and their Clones
jdfan1000
Posts: 81
Joined: Tue Aug 02, 2016 8:06 pm
Location: Buffalo, NY
Contact:

Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by jdfan1000 »

Yes, I think for a while. Wes was an engineer at IBM. The group was located in the area that included IBM's headquarters.

He also wrote some great articles about interrupts and about the bank switching in the 2068.

David
My archive.org collection, containing many Timex/Sinclair related publications.

TimexSinclair.com, my website about Sinclair computers in the US.
David G
Posts: 387
Joined: Thu Jul 17, 2014 7:58 am
Location: 21 North, 156 West

Exploring the ULA - Pinout

Post by David G »

PAGE 4 SINCUS NEW JAN/FEB 89

EXPLORING THE TIMEX/SINCLAIR 1000'S
SINCLAIR LOGIC CHIP
( SCL )
PART 2
by
Don Lamen, SINCUS
6-29-88

Simulation Circuits and Timing Charts of the SCL Chip

Being unable to draw the exact circuits; because of the lack of any technical
data on the Ferranti Mask Programmable Universal Logic Chip ULA2C184E (either
programmed or unprogrammed); using standard TTL chips I have made the following
drawings simulating the functions that the ROM routines indicate.

ULA2C184E Pin-out Chart 1C-1 SCL CHIP

Code: Select all

1   A7' --->        40  +5V
2   A8' --->        39  A6' --->
3   A2' --->        38  A5' --->
4   A1' --->        37  A4' --->
5   A0' --->        36  A3' --->
6   RD <---         35  CLOCK
7   IORQ <---       34  GND
8   WR <---         33  KBD0 <---
9   MREQ <---       32  DO <--->
10  M1 <---         31  KBD1 <---
11  A14 <---        30  D1 <--->
12  RAMC.S. --->    29  KBD2 <---
13  ROMC.S. --->    28  D2 <--->
14  CLOCK' --->     27  KBD3 <---
15  NMI --->        26  D3 <--->
16  TV/TAPE --->    25  KBD4 <---
17  HALT <---       24  D4 <--->
18  A15 <---        23  D5 <--->
19  D7 <--->        22  USA/UK <---GRD FOR USA
20  TAPE IN <---    21  D6 <-->

fclock = 6.5 Mhz
fclock' = 3.25 Mhz
Editor's note: Due to the amount of drawing, several will be included in the Mar/Apr 89 issue of SINCUS NEW, with the rest of Don's notes.
In the above artwork- there are lines over RD, WR, MREQ, RAMC.S., ROMC.S., HALT NMI, and M1.
David G
Posts: 387
Joined: Thu Jul 17, 2014 7:58 am
Location: 21 North, 156 West

Exploring the ULA - Scan Line Timing diagram

Post by David G »

Reading the second issue of the newsletter, I started wondering how he got all the data. Then I remembered you said
jdfan1000 wrote: Sun Sep 04, 2022 3:08 amWes was an engineer at IBM.
Wes may have had his own oscilloscope and precision tools, and the discipline of how to carefully document the work?

SINCUS NEW JAN-FEB 89 PAGE 5

ONE SCAN LINE 414T 63.69u Sec.
Refer to Part I, page 5 (Nov/Dec 88 SINCUS NEWS)
"Prime Clue in Timing"
ONE SCAN LINE 414T 63.69u Sec..jpg
David G
Posts: 387
Joined: Thu Jul 17, 2014 7:58 am
Location: 21 North, 156 West

Exploring the ULA - U3 Timing and Circuit for Dot Oscillator

Post by David G »

PAGE 6 SINCUS NEW JAN-FEB 89

U3 TIMING
U3 TIMING.jpg

SIMULATION OF THE DOT OSCILLATOR
SIMULATION OF THE DOT OSCILLATOR.jpg
Refer to Part I, page 5-6 (Nov/Dec 88 SINCUS NEWS)
"Dot Oscillator"
David G
Posts: 387
Joined: Thu Jul 17, 2014 7:58 am
Location: 21 North, 156 West

Exploring the ULA - Circuit for Timing Chain

Post by David G »

SINCUS NEW JAN-FEB 89 PAGE 7

SIMULATION OF TIMING CHAIN
SIMULATION OF TIMING CHAIN.jpg
Refer to Part I, page 6 (Nov/Dec 88 SINCUS NEWS)
"Internal Timing Chain"
Moggy
Posts: 3231
Joined: Wed Jun 18, 2008 2:00 pm

Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by Moggy »

This may interested you, it has been posted before but time for a refresh.

It's in French and the interesting bit starts at about the 7.5 minute mark.

Also some Ferranti literature concerning the 2000 series ULA's

https://archive.org/details/FerrantiULA ... t/mode/2up

https://www.youtube.com/watch?v=fxLtgs- ... ExSilicium
Moggy
Posts: 3231
Joined: Wed Jun 18, 2008 2:00 pm

Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by Moggy »

Somewhere I have some pictures of the ULA cells from a decapped ULA and I'm sure I posted them at some point in time.
David G
Posts: 387
Joined: Thu Jul 17, 2014 7:58 am
Location: 21 North, 156 West

Exploring the ULA - Intercept Circuit

Post by David G »

I'm thinking this is the intercept of the data lines when the ULA is generating the video signal?
The Intercept Control Circuit controls the flow of signals on the Internal Data Bus and Screen Inversion.
PAGE 8 SINCUS NEW JAN-FEB 89

INTERCEPT CIRCUIT
INTERCEPT CIRCUIT.jpg
Refer to Part I, page 7-8 (Nov/Dec 88 SINCUS NEWS)
David G
Posts: 387
Joined: Thu Jul 17, 2014 7:58 am
Location: 21 North, 156 West

Exploring the ULA - Parameters & Interrupt Timing

Post by David G »

Conclusion of installment 2
SINCUS NEW JAN-FEB 89 PAGE 9

PARAMETERS

Code: Select all

Dot Clock Frequency: 6.5 MHz + or - 200 Hz
Processor Clack Frequency: 3.25 MHz + or - 100 Hz
Dot Period (Td}: 0.1538451 uSec. + or - 4.7 pSec.
Processor Clock Period (Tp): 0.3076923 uSec. + or - 9.4 pSec.
Horizontal Sync Pulse: 19.Tp = 5.85 uSec.
Horizantal Scan Line: 207 Tp = 63.69 uSec.
Frame Sync Pulse:  1212 Tp = 372.92 uSec.
One Frame: 54234 Tp = 16687.384 uSec.
           1/60 Sec. = 16666.6 uSec.
Therefore: The Frame Time is 0.12 % Slow, well within the allowable 2 %.
Normal Horizontal TV Scan = 63.4 uSec.
Therefore: The Horizontal. Scan Time of the T/S 1000 (63.69 uSec.) is 0.46 % Slow, also well within the allowable 2 % .
NOTE: After the first Frame, each Frame equals exactly 262 ScanLines.

INTERRUPT TIMING

NMI:

1. If NOT NMI is Low and NOT HALT is Low the Instruction Execution Time 11 Tp (The
Same as a normal RST instruction).
2. If NOT NMI is Low and NOT HALT is High the Wait circuit built around transister
TR-1 pulls the NOT WAIT Pin of the Z-80 Low. The M1 cycle of the NMI instruction
dees not poll the NOT WAIT Pin. Therefore the NOT WAIT signal is not detected until T2 of M2, a WRITE cycle, which is the 7th T cycle of the instruction. This leaves 5 T cycles to be completed after the NOT NMI Pin goes High. Therefore, the
execution time of this instruction is equal to the Horizontal Sync + 5 Tp (24 Tp).

INT:

1. In Interrupt Mode 0 the execution time is 2 Tp more than the normal execution
time for the instruction being entered by the peripherai. This is because there
are two built in wait states in this interrupt.
2. In Interrupt Mode 1 the execution time is 13 Tp, two more than a nermal RST
instruction because of the two built in wait states.

3. In Interrupt Mode 2 the execution time is 19 Tp. 4. The Maskable Interrupt polls
the NOT WAIT fine on the 2nd built in WAIT T cyle of M1. If the NOT WAIT line is
pulled Low late it can also be detected during TZ of either M2 or M3.

NOTE:
1. Both NMI and INT have a Ti, T2, T3, T4 & T5 in M1 and T1, T2 & T3 in both M2
& M3.
2. In INT the built in wait states are between T2 & T3 of M1.

Part 3 will conclude this series on the TS1000 SCL Chip in the Mar/Apr 89 issue.
jdfan1000
Posts: 81
Joined: Tue Aug 02, 2016 8:06 pm
Location: Buffalo, NY
Contact:

Re: Exploring the ULA - Scan Line Timing diagram

Post by jdfan1000 »

I’m not sure what equipment Wes had access to… he’s done some hardware work related to the 1000 and 2068. Most of his published stuff is about the bank switching in the 2068 and interrupts.
My archive.org collection, containing many Timex/Sinclair related publications.

TimexSinclair.com, my website about Sinclair computers in the US.
Post Reply