Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

General Chit Chat about Sinclair Computers and their Clones
Moggy
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Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by Moggy »

A PDF of one persons exploration of the workings of the ULA (2c184 in this case)

The article runs from page 4 of the PDF.

https://ia601304.us.archive.org/27/item ... 7%20n1.pdf

The article apparently was concluded in further issues but should be of interest anyway.

The further issues can be found here along with the rest of the magazine collection, the article continues from Vol 7 issue 2..

https://archive.org/details/SincusNews/ ... 20v1%20n1/
David G
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by David G »

Nice find. So much technical info on the ZX81's ULA


This is the first time i am hearing anyone say this:
Since 1940 I have worked and played with computers

Now, considering that in 1980 the most popular micros were S-100 types... this is very interesting
[early in 1982] I was building my own computer based on the S-100 bus using the Z-80 microprocessor...I discovered that the little TS-1000 with a 16K RAM pack would do a lot more than the computer that I was building. The whole TS-1000 system cost less than what I had spent building one 8K RAM board and the power that it used was next to nothing. Needless to say my S-100 computer construction stopped the day I bought the TS-1000.
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Moggy
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by Moggy »

If he'd have said he had been playing with computers from say 1945 onwards I would believe him but 1940 no, unless he meant some crude analogue system, seeing as Colossus the worlds first recognised digital computer didn't see the light of day till 1943 and the worlds first stored program computer, the Manchester Baby, didn't arrive till 1948.


I once had some benchmark tests (now lost) for Forth based systems from back then and the best of the bunch was a Z80 4Mhz S100 bus set up. I ran the benchmarks on a ZX81 using Toddy Forth and it it left the 4Mhz system in the dust, which isn't bad for a computer running at a quarter Megahertz slower and reckoned to be technically inferior.
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1024MAK
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by 1024MAK »

Wow Moggy, I’m surprised. If the S100 system had enough RAM and the Forth was well written, it should have beaten the Zeddy.

It just goes to show that you can’t just go on looks or cost :lol:

Mark
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Moggy
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by Moggy »

Agreed Mark also faster than the Ace too, but to be fair the kind of Forths offered to the hobby community back then where not the best efficiency wise and were probably using a generic indirect threaded code ported between systems various, rather than the direct threaded code of Toddy aimed at a specific machine which Kelly has had many years to refine without a rush to market unlike the situation back then. Even a hardware Forth such as Pluri-Forth/H4th is slow compared to Toddy as well as being non standard in much of its implementation.

Kelly's efforts with Toddy over time especially the Forth-79 version are Herculean and I say that as someone who was the biggest and perhaps meanest critic of Toddy some 10 years ago. Glad to say he didn't take my mean spirited mutterings to heart even to the point of asking me to test some small parts of the language (including at last a fast type rate, key repeat Memotech suitable keyboard routine), a language which I cannot see my self ever forgoing as it has given me so much pleasure allowing as it does the Zeddy to punch above its weight mathematically which is where my interest lies, and renewed my love for the little door wedge.
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1024MAK
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by 1024MAK »

Ah, well, I was blissfully unaware that so much work, love, sweat and tears had gone into Toddy Forth… That would definitely make a big difference. As you say, it’s been improved and optimised over time 8-)

Mark
ZX81 Variations
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Exploring the ULA/SCL installment one

Post by David G »

I had a basic undertanding of the ZX81 ULA, but this article seems to take it to an expert level. The first chapter focuses on the logic rather than the circuitry.

Cover of SINCUS NEWS newsletter dated November/December 1988
NOV/DEC 1988 VOL VII: NO. 1

-----------------------------------------------------
the newsletter of the Sinclair Computer Users Society
-----------------------------------------------------
SINCUS NEWS
1229 Rhodes Road
Johnson City, New York 13790
-----------------------------------------------------
Since 1982
-----------------------------------------------------

Page 4.............Part 1, 1000's SCL map
article starting on page 4
Page 4 SINCUS NEWS NOV/DEC 88

EXPLORING THE TIMEX/SINCLAIR 1000'S
SINCLAIR LOGIC CHIP
( SCL )
by Don Lamen, SINCUS 6-29-88

ACKNOWLEDGEMENTS:
Toni Baker's book "Mastering Machine Code On Your ZX/81" was a big help in disassembling the ROM code and printing it out.

Dr. Ian Logan's & Dr. Frank O'Hara's book, "The Complete Timex TS 1000 / Sinclair ZX 81 ROM Disassembly" was a big help in understanding what I had printed out.

National Semiconductor's "TTL Data Book" made it possible to select the standard ICs for drawing the simulation circuits.

Zilog's Technical Manual on the Z-80 Microprocessor was very helpful, in this study, as to timing.

Time Designs Magazine for clarifying some points pertaining to the I/O section and the Frame sync timing.

There are many others who have added to my knowledge and understanding.

I wish to thank one and all for their many contributions.

----------------------------
The History and The Problem:

Early in 1982, I believe in either February or March,I bought my first TS-1000 computer. At the time, I was building my own computer based on the S-100 bus using the Z-80 microprocessor as the CPU. I bought the TS-1000 intending to use it to write the ROM and Character Generator for the computer that I was building.

When I plugged it in and tried it out I discovered that the little TS-1000 with a 16K RAM pack would do a lot more than the computer that I was building. The whole TS-1000 system cost less than what I had spent building one 8K RAM board and the power that it used was next to nothing. Needless to say my S-100 computer construction stopped the day I bought the TS-1000.

Now I have seven computers and four of them are Timex / Sinclair computers. All of the Sinclair computers are excellent computers and with the proper peripherals they will measure up to anything on the market in the microcomputer field. These computers are also very portable. Since 1940 I have worked and played with computers, Mainframes, Minnies and micros. We have come a long way since the old 6SN7 flip-flops.

Now for the problem part. It is my opinion that in order to get maximum utility from any device you need to know exactly how it works. Since the day I bought my first TS-1000 to the present, I have read everything I could get my hands on trying to obtain an accurate understanding of the Sinclair Logic Chip. There are many viewpoints and different opinions about the functions of this chip.

On April 7, 1988 I decided to use the ROM routines to try and discover just what the SCL does and how it does it. The following is the result of that attempt. There may be some errors or oversights or misconceptions. If anyone wishes to comment pro or con or has questions or something to add feel free to write me. If you desire a return letter, please include a SASE. My address is: DONALD B. LAMEN, RD 3 - BOX 3404, WINDSOR, NEW YORK 13865 .
COMMENTS: SCL is another name for the Sinclair ZX81 ULA (specifically, SCL is the name used by Timex/Sinclair). This is the chip that replaced most of the motherboard logic of the ZX80. The ULA was the reason the ZX81 was inexpensive yet as powerful as more expensive early home computers. Only the minimal video and keyboard kept the ZX81 from being a true powerhouse of usability. But just a year later the Commodore VIC20 arrived and two years later the Commodore 64 came out, and due to the march of technology those were more useful machines. Any yet even so, i heard that the ZX81 was history's top-selling computer until the Commodore 64 came out (is that accurate?) The ZX81 had minimal sales in the USA but when Timex marketed it (as the TS1000) they sold many, many on price alone -- even in the presence of the C64.

one thing to understand reading this article are the M1 and A15 lines in the ZX81. These lines of the Z80 are intercepted and used for the video generation circuitry, resulting in a quirk of the ZX81 not being able to execute code located in the top half of memory (this quirk can be overcome by a simple hardware modification called M1NOT).
SINCUS NEWS NOV/DEC 88 Page 5

THE RESULTS

Prime Clue In Timing:

While running the display routines on paper, keeping tract of the timing in microprocessor T cycles, I discovered that each character row scan line takes 207 T cycles. This the key to the entire timing chain.

Taking 207 T cycles as the length of each scan line and going through the entire display routines (including frame sync) I was able to resolve the length of the horizontal sync pulse. The horizontal syncpulse takes 19 microprocessor T cycles.

To understand the Logic Chip we must remember that it is timed by the Dot Clock which is twice as fast as the Microprocessor Clock. Therefore, one scan line is 414 Dot Cycles, the horizontal sync is 38 Dot Cycles, etc..

The SCL Chip:

The SCL Chip is a Mask Programable Universal Logic Array (ULA 2C184E ) made by Ferranti in Italy. This chip is programed at the time of manufacture by Photo-Masked deposition according to a table prepared by the equipment manufacturer (Sinclair). The SCL Chip provides the following functions and/or circuits:

a) Dot Oscillator and Internal Clock
b) Microprocessor Clock
c) Internal Timing Chain
d) Horizontal Sync Generator
e) Character Scan Line Counter_3 bit
f) Internal Data Bus
g) Intercept Control Circuit
h) Internal Data Latch
i) No-Op Generator
j) Two Shift-Registers 8 bit, each
k) Input I/O Port FE_7 bit
l) ROM-Driver Buffer_9 bit
m) I/O Decoder
n) NMI Generator
o} Frame (Vertical) Sync Generator
p) Video Combiner and Inverter Circuit
q) ROM/RAM Select Circuit

The purposed function diagram of the ULA 2C184E chip (SCL) goes here.


DESCRIPTIONS OF THE FUNCTIONS

Dot Oscillator:

The Dot Frequency is controlled and stabilized by a 6.5 MHz ceramic filter used as a crystal in a Series resonant circuit. A circuit external to the SCL chip. There is also a series capacitor and a shunt resistor in this circuit.

Refering to the simulation circuit presented further on, the resistor R1 being across the crystal and the capacitor C1 will lower the Q of the circuit broadening the resonance. This helps mask any jitter caused by switching within the chip. Also R1 in conjunction with R2 sets the bias and operating point of the transistor. C3 and C4 being across the filter tends to lower the frequency of oscillation while C1 tends to increase the frequency. The ratio of C3 to C4 determines the amount of feedback.
At this point I was quite confused, so I looked up the TV timing signals. Line Sync pulse is 4.7 microseconds for TV (PAL and NTSC and Composite). However I was not able to correlate this 4.7usec to the Dot Cycles timings he lists
Page 6 SINCUS NEWS NOV/DEC 88

Microprocessor Clock:

The Microprocessor Clock is the Dot Frequency divided by two (3.25 MHZ) and inverted. This may be generated by a single flip-flop using the Dot Clock both as a clock and as an input. However, it is probably taken from the first stage of the timing chain counters. External to the SCL chip is a circuit built around transistor TR2 which buffers the Processor Clock and re-inverts it.

Internal Timing Chain:

The Internal Timing Chain must provide the following functions:

a) Divide the Dot Clock by two to provide the Processor Clock signal.
b) Provide Turn-On and Turn-Off pulses to the Horizontal Sync Flip-Flop, to generate the Horizontal Sync pulses with a duration of 38 Dot cycles, at the beginning of each TV scan line.
c) Provide a four bit binary counter (divide by 16). The first three bits of this counter provides the timing for the Intercept Circuit and the first bit may also furnish the signal for the Processor Clock, which would then be inverted and sent to Pin 14. The forth bit is-used to multiplex the two Shift-Registers. The counter's Carry—Out (Overflow) enables the next counter in the string for ONE count.
d) Provide a second five bit binary counter (divide by 32). By presetting the first counter to the value of 2 and this second counter to the value of 6 and NANDing bit 4 of the first counter with bit 4 of the second counter we obtain our Turn-Off pulse for the Horizontal Sync Generator. The Carry-Out of this second counter provides the Horizontal Sync Turn-On pulse terminating the scan line. This Carry-Out pulse also advances the Character Scan Line Counter and presets the Main Timing Chain, thereby starting the next scan line of 414 Dot cycles. (In the simulation two 4 bit counters are substituted for the 5 bit counter with the Carry-Out of the second counter enabling the third counter and the third counter's Carry-Out taking care of the termination chores. The third counter is preset to 14.)

Horizontal Sync Generator:

The Horizontal Sync Generator is basically a flip-flop which is turned on and off by the Main Timing Chain. The Output of the Horizontal Sync Generator supplies the Horizontal Sync Pulse to the Video Combiner Circuit. It also supplies the source Signal for the NMI Generator and one of the control signals for the Intercept Circuit. These pulses are 38 Dot cycles long and come from the Q output of the flip-flop.

Character Scan Line Counter:

The Character Scan Line Counter is a 3 bit binary counter (A 4 bit counter is shown in the simulation, but only the first 3 bits are used). This counter is reset by a reset Signal which is generated by the Frame Sync Generator and is held in the reset mode until the end of the Frame Sync Pulse. This is necessary because the number of Dot cycles in a scan fine is not evenly divisible by eight (the number of scan lines in a character row) and holding the reset affords a method of resyncronizing the counter. The counter is advanced one count at the completion of each scan line. The output of Bits 1 to 3 (count from 0 to 7) is fed through the first 3 bits of the ROM Driver Buffer (a 9 bit tri-state buffer) to Address Lines AO' to A2'.
What is "over—lined"? Does he mean that "HALT" and "M1" should be typeset in the newsletter article as "M1" with a line over it (overline, M̅1̅) ?
SINCUS NEWS NOV/DEC 88 Page 7

Internal Data Bus:

There is an Internal Data Bus connected to DO through D7 (8 lines), which carries data to and/or from the following:

a) Internal Data Latch
b) NoOp Generator
c} Two Shift-Registers_8 bit each
d} Input Port FE_7 bit
e) Lines D6 & D7 to Intercept Control

Intercept Control Circuit:

The Intercept Control Circuit controls the flow of signals on the Internal Data Bus and Screen Inversion. It's Timing and Control signals come from the following sources:

a) The first counter of the Main Timing Chain
b) A15
c) M1
d) The Horizontal Sync Generator
e) HALT
f) D6
g) D7

Note: M1 in item (c) and HALT in item (e) should both be over—lined.

The timing counter bits are weighted as follows:

Bit-1 ----- 1
Bit-2 ----- 2
Bit-3 ----- 4
Bit-4 ----- 8

The Intercept Control Circuit consists of the following circuits and/or components:

a) 6 Timing Decoders
1. Multiplex Timing (Code 8 or Code NOT 8)
2. Sensing (Code positive edge of 2 AND NOT 4)
3. Latch-In (Code 1 AND 2 AND NOT 4)
4. No-Op (Code NOT 2 AND 4)
5. Latch-Out (Code 2 AND 4) inverted
6. Load (Code 1 AND 2 AND 4)
b) 3 Flip-Flops
1. Intercept Flip-Flop
2. Inverse Flip-Flop 1
3. Inverse Flip-Flop 2
c) 3 Reset Gates
1. Intercept Reset Gate
2. Inverse Reset Gate 1
3. Inverse Reset Gate 2
d) 2 Multiplexed Clock Gates
1. Inverse Clock Gate 1
2. Inverse Clock Gate 2
e) 1 Iverse OR Gate
f) 2 Multiptexed Shift-Register Load Gates (1&2)
g) 6 Inverters
Page 8 SINCUS NEWS NOV/DEC 88

The Intercept Control Circuit works as follows:

The timing of this circuit is controlled by the first counter of the Main Timing Chain, which counts from 0 to 15 overand over except when preset. When preset to 2 it counts from 3 to 15 then goes to 0 (14 counts). Each time this counter returns to 0 it puts out a Carry-Out to the next counter.

On the rising edge the counter's T-cycle 0 (Code NOT 8) the Shift-Registers are switched and Shift-Register 1 becomes inhibited. On the rising edge of the counter's T-cycle 8 (code8) the Shift-Registers are switched back, Shift-Register 2 becoming inhibited. The Uninhibited Register now shifts out it's eight bits of data to the Video Combinor.

The inhibit signal is delayed for about a half a Dot cycle the active shift-register time to shift out it's last bit.

The NOT M1 signal is Inverted and ANDed with the Signal on A15 then fed to the 'D' input of the Intercept Flip-Flop. At the rising edge of Dot-Cycle 2, of the character set of 3 Dot cycles, (Code 2 AND NOT 4) the signal on the 'D' input is clocked in. If NOT M1=0 AND Al5=1 the Intercept Flip-Flop is SET otherwise it is RESET. SETing the Intercept Flip-Flop enables the rest of the timing gates, except for MUX which is always enabled.

During Dot cycle 3 (Code 1 AND 2 AND NOT 4) the data on the Data Bus lines D0 through D5 will be latched into the Internal Latch and the contents of D7 will be clocked into Inverse Flip-Flop 1 if Code NOT 8 or into Inverse Flip-Flop 2 if Code 8. However, if D6=1 (or NOT HALT=0 or during Horizontal Sync), then the Intercept Flip-Flop will reset, disabling the intercept and allowing the Z80 to read the HALT instruction as usual.

During Dot cycles 4 & 5 (Code NOT 2 AND 4) the No-Op Generator is enabled forcing all eight Data lines to 0. The Z80 reads the No-Op instruction. and fetches the next byte from the memory.

During Dot cycles 6 & 7 (Code 2 AND 4), while the Z80 is decoding the No-Op instruction and refreshing the memory, the Intercept Circuit enables the Tri-state Output Buffer (ROM Driver), putting the Output of the Character Scan Line Counter on Address Lines A0' through A2' and the Latched Data (Character Code) on Address Lines A3' through A8'. At the same time the Address Lines A9 through A15 contains a copy of the contents of the I Register. This accesses the Dot Code from the ROM, which the ROM places on the Data Bus.

During Dot cycle 7 the 8 bit Dot Code on the Data Bus is Loaded into the inhibited Shift-Register.

During Dot cycle 8 the Shift-Registers are switched and the same operations are repeated, but on the opposite Shift-Register.

-----------------------------------------------------
Rest of article and artwork to follow in next issues.
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by jdfan1000 »

I’m glad you found and are enjoying these! I was thrilled to get these old newsletters and scan/post them to archive.

Btw, Wes Brzozowski is still around. He recently joined us for a chat on your zoom group. The recording is on Youtube.

David
My archive.org collection, containing many Timex/Sinclair related publications.

TimexSinclair.com, my website about Sinclair computers in the US.
David G
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by David G »

Yes thank you for scanning these treasures
David G
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Re: Exploring the Timex/Sinclair 1000’s Sinclair Logic Chip (SCL)

Post by David G »

jdfan1000 wrote: Sat Sep 03, 2022 3:55 amBtw, Wes Brzozowski is still around. He recently joined us for a chat on your zoom group. The recording is on Youtube.
he was secretary for SINCUS?

thanks for the tip - i just looked his articles over and typed one into the Type-Ins thread
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