Sinclair ZX80 / ZX81 / Z88 Forums

Hi Retrotechie, I have had a look at a fully functional zx81 in particular the wait pin on the z80. In slow mode, negative going pulses on the wait pin but to my surprise the pulses do not fall to ground, instead from 5V to around 1.5V in depth. So what I did was include some emitter degeneration re...

That's a question I didn't see fully answered so far: does the machine hang always when NMI's are passed through (no matter what else you do), or is it screen corruption only? Hi Retrotechie, The slow mode is quite unstable and so upon multiple global resets it falls on quite a few different states...

Hi all,

Tested the nop generator today, agree's 100% retrotechie's timing diagrams perfect.

Cheers
Commie

IIrc that's "clock enable" but is kinda the same thing in this context.. ;) Okay yeah kinda the same thing but it makes more sense now because it just means the clock is gated with ce. I was wondering though: in a ZX81 the hsync pulses come at 207-cycle intervals. Logic decoding the counter bits ju...

PokeMon wrote: Did you use the 47pF capacitor in parallel to the 10k resistor as well ?
It seems that the transistor doesn't switch fast enough and is probably saturated.

I tried a whole range of capacitors and resistors, also I built the circuit using an 'or' and inverter gates and still just the same result.

Could you post this schematic detail and type of transistor ? PokeMon, I don't have the schematic in a file right now but look on any zx81 schematic and locate Tr1, the transistors I've tried are PN2222A and 2N2369A, both give the same results, I have also varied the relavent resistor values to exh...

Hi Folks, Just some extra info which might help, the t state synchroniser which is a npn bjt emitter=nmi, collector (via 1k resistor)=cpu wait and base (via 10k resistor)=halt. If I remove the halt 10k base resistor then wait states are no longer activated, with this resistor out of circuit, I get a...

It would be interesting to see what happens when switching NMI on and off if this brings your system to crash even if NMI is not connected and so NMI can not occur from sight of the CPU. Up to you - just a proposal if you are interested in solving this problem. If not, is okay for me. ;) PokeMon, I...

Aiiii... so you may have timing differences between 3.25 MHz clock edges inside the CPLD, and clock edges the Z80 sees? That might be bad. :x Or not. :?: Dunno. In my CPLD design I put both 3.25 MHz signals on global clock pins of the CPLD, meaning flip-flops clocked by the same clock edge are cloc...

This way you could start up in FAST mode while keeping NMI pin high and try **OUT 254,0 for switching NMI on and **OUT 253,0 for switching it off. As I understand you?, I think I've already tried something similar, with the nmi tied high boot up then connect the nmi then type 'slow' mode in basic a...