Sinclair ZX80 / ZX81 / Z88 Forums

The analyser trace shows this to be clocked by a free-running oscillator at a frequency of just over 6kHz on the ULA I have. Mystery indeed seemingly solved. FWIW I've measured the outputs from a4, a5 and a6 carefully, using an idea from Mark where the /RFSH line is pulsed via the Z80 clock. It's e...

Finding #0: It draws about 0.46-0.50A at +5V and operates at about 35oC. Do you really mean 460mA to 500mA :shock: Despite this thing glowing at 35oC, I was missing a zero :oops:. The ULA draws about 50mA . Good catch! Finding #1: Every time /RFSH pulsed active, some apparently internal value is pr...

Don’t forget the Z80 still increments the refresh register (R) with every instruction fetch (including during HALT) and outputs this on address lines A0 to A7 (although bit 7 does not change unless the program changes it). And as the display system is not used during FAST mode, this normal Z80 refr...

Thanks Mark ! Well this answers one question I had concerning the 128 x 128 DRAM matrix which was how come the rows were assigned the 7-bit value from A6..A0 and the columns A13..A7. For any brave souls following along, in theory the other way around might seem cleaner i.e. A13..A7 rows, and A6..A0 ...

In all cases each data line (D0 to D7) goes to the data line (input and output) connections on each DRAM chip. Address lines A0 to A13 (for ZX81) go to two 74LS157 "two to one line selector" chips. The outputs from the 74LS157's go to all the DRAM chips. Note that the Z80 address lines A0 to A6 hav...

I've been investigating the Ferranti ULA 1H035E used in the ZX81 RAM pack Issue 3. One aspect of this that is as yet a mystery to me is how the DRAM in this particular RAM pack is refreshed. For the Issue 1, an analysis of the schematic that is widely floating around shows the following. I think. (T...

Before responding to your question, Mark I wanted to verify my implementation of PokeMon's circuit is OK. Having scoped it a bit, I'm not so sure it's behaving as intended. Quick theory recap: 00.. .... .... .... ROM 0000 01.. .... .... .... RAM 4000 - normally the onboard 1K 10.. .... .... .... ROM...

This ULA is currently the bane of my existence. See: viewtopic.php?f=7&t=4266&p=43485#p43485

@RetroTechie: Did you get further with your analysis? I'm kinda wondering how to recreate one of these... shudder.

Ah yes, decoupling the IC power from the main power supply. For fun, I put a scope on the power to observe the effect of adding these capacitors: Before: Existing power.jpg After: Power both.jpg Then I did a slight variation on your program: Prog.jpg And measured the /CAS line on the RAM pack: CAS j...

Well the results are in, and they are err not so good. In summary, it's like the memory addresses $8000..$BFFF (i.e. the RAM pack memory) always return $FF. Normal.jpg FLIR.jpg See attached picture of implementation (meticulously checked for connections), where top board is a composite video thing a...