Search found 176 matches

by McKlaud
Sat Nov 10, 2018 9:44 pm
Forum: Hardware
Topic: ROM cartridge
Replies: 3
Views: 120

Re: ROM cartridge

by McKlaud
Sat Nov 10, 2018 9:20 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

No /IORQ, no /NMI ...
by McKlaud
Sat Nov 10, 2018 9:03 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

by McKlaud
Sat Nov 10, 2018 8:51 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

well, this is not the case in my ULA, because I've got pull-ups and pull-downs there.
by McKlaud
Sat Nov 10, 2018 7:17 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

Gents, correct me if i am wrong, but there is no NMI generation at all when the ZX80_81 is pulled down. The quoted numer of 55 or 31 indicates how many scanlines should be generated and this value is read from ROM and held under the system variable called MARGIN. The MARGIN value is driven by the ot...
by McKlaud
Sat Nov 10, 2018 2:56 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

Mark,

Thanks for ideas, but I've tried my ULA it two different board. One was fitted with newer 27C64 chip with programmed the latest ROM. The same issues on both PCBs.
by McKlaud
Sat Nov 10, 2018 12:51 pm
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

Looking at your snapshots, the NMI generation was re-entered successfully a few times and then stopped The is something weird going on. I think the same is going on in my case.
by McKlaud
Fri Nov 09, 2018 1:08 am
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

Bear in mind that the main difference between ZX80 and ZX81 is this NMI generator. Disabling it via pulling ZX80_ZX81 line down, you block the NAND gate regardless of status of Hsync and NMI_on lines. The NMI_on is latched and started by /IORQ, /WR & A0 being low (any value sent to port 0xFE) and cl...
by McKlaud
Fri Nov 09, 2018 12:17 am
Forum: Welcome Area
Topic: Hello from Spain
Replies: 9
Views: 239

Re: Hello from Spain

hi Manuel :)
by McKlaud
Fri Nov 09, 2018 12:15 am
Forum: Development
Topic: ZX81 ULA-in-a-CPLD
Replies: 233
Views: 26374

Re: ZX81 ULA-in-a-CPLD

Following Alvin's documents 1/ Hsync generation is shown below. 2/ Regarding NMI generation Next to it 2 flip-flops that control the software-generated vertical sync, and whether the Z80 receives NMI's. A high input on "zx80_zx81" lets NMI's pass through as in a ZX81, a low input disables NMI's as i...