Design Name | zx81_ula |
Device, Speed (SpeedFile Version) | XC9572, -15 (3.0) |
Date Created | Sat May 5 02:09:28 2012 |
Created By | Timing Report Generator: version O.87xd |
Copyright | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
---|
Possible asynchronous logic: Clock pin 'NMI_on.CLKF' has multiple original clock nets 'Wr' 'Iorq' 'a0'. |
Possible asynchronous logic: Clock pin 'vsync.CLKF' has multiple original clock nets 'NMI_on.Q' 'Iorq' 'Rd' 'a0'. |
Possible asynchronous logic: Clock pin 'a1.CLKF' has multiple original clock nets 'hsync_sym/q7.Q' 'hsync_sym/q6.Q' 'hsync_sym/q5.Q' 'hsync_sym/q4.Q'. |
Possible asynchronous logic: Clock pin 'a2.CLKF' has multiple original clock nets 'hsync_sym/q7.Q' 'hsync_sym/q6.Q' 'hsync_sym/q5.Q' 'hsync_sym/q4.Q'. |
Possible asynchronous logic: Clock pin 'a0.CLKF' has multiple original clock nets 'hsync_sym/q7.Q' 'hsync_sym/q6.Q' 'hsync_sym/q5.Q' 'hsync_sym/q4.Q'. |
Performance Summary | |
---|---|
Min. Clock Period | 44.500 ns. |
Max. Clock Frequency (fSYSTEM) | 22.472 MHz. |
Limited by Cycle Time for cpuclk_OBUF.Q | |
Clock to Setup (tCYC) | 44.500 ns. |
Pad to Pad Delay (tPD) | 39.500 ns. |
Setup to Clock at the Pad (tSU) | 37.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 75.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS_osc | 24.0 | 23.5 | 1 | 0 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
Xin to Xout | 24.000 | 23.500 | 0.500 |
Clock | fEXT (MHz) | Reason |
---|---|---|
Wr | 71.429 | Limited by Clock Pulse Width for Wr |
NMI_on.Q | 71.429 | Limited by Clock Pulse Width for NMI_on.Q |
Iorq | 71.429 | Limited by Clock Pulse Width for Iorq |
Rd | 71.429 | Limited by Clock Pulse Width for Rd |
a0 | 71.429 | Limited by Clock Pulse Width for a0 |
cpuclk_OBUF.Q | 22.472 | Limited by Cycle Time for cpuclk_OBUF.Q |
Xin | 71.429 | Limited by Clock Pulse Width for Xin |
clk_6m5.Q | 37.736 | Limited by Cycle Time for clk_6m5.Q |
cpuclk_inv_OBUF.Q | 52.632 | Limited by Cycle Time for cpuclk_inv_OBUF.Q |
hsync_sym/q7.Q | 52.632 | Limited by Cycle Time for hsync_sym/q7.Q |
hsync_sym/q6.Q | 52.632 | Limited by Cycle Time for hsync_sym/q6.Q |
hsync_sym/q5.Q | 52.632 | Limited by Cycle Time for hsync_sym/q5.Q |
hsync_sym/q4.Q | 52.632 | Limited by Cycle Time for hsync_sym/q4.Q |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
Iorq | 37.000 | 0.000 |
M1 | 37.000 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
Mreq | 31.000 | 0.000 |
border | 5.500 | 0.000 |
d0 | 5.500 | 0.000 |
d1 | 5.500 | 0.000 |
d2 | 5.500 | 0.000 |
d3 | 5.500 | 0.000 |
d4 | 5.500 | 0.000 |
d5 | 5.500 | 0.000 |
d6 | 5.500 | 0.000 |
d7 | 5.500 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
Halt | 11.500 | 0.000 |
M1 | 11.500 | 0.000 |
Mreq | 11.500 | 0.000 |
a15 | 11.500 | 0.000 |
d0 | 11.500 | 0.000 |
d1 | 11.500 | 0.000 |
d2 | 11.500 | 0.000 |
d3 | 11.500 | 0.000 |
d4 | 11.500 | 0.000 |
d5 | 11.500 | 0.000 |
d6 | 11.500 | 0.000 |
d7 | 11.500 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
Csync | 44.000 |
luminance | 44.000 |
Nmi | 37.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
Csync | 44.000 |
luminance | 44.000 |
Nmi | 37.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
Csync | 37.500 |
luminance | 37.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
Csync | 44.000 |
luminance | 44.000 |
Nmi | 37.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
a3 | 75.500 |
a4 | 75.500 |
a5 | 75.500 |
a6 | 75.500 |
d1 | 75.500 |
d2 | 75.500 |
d3 | 75.500 |
d4 | 75.500 |
d6 | 75.500 |
a0 | 68.000 |
a1 | 68.000 |
a2 | 68.000 |
a7 | 68.000 |
a8 | 68.000 |
d0 | 68.000 |
d7 | 68.000 |
Ramcs | 59.500 |
Romcs | 59.500 |
luminance | 59.500 |
Csync | 52.000 |
Nmi | 52.000 |
d5 | 50.000 |
cpuclk | 26.000 |
cpuclk_inv | 26.000 |
Source | Destination | Delay |
---|---|---|
hsync_sym/q1.Q | hsync_sym/XLXI_2/Q0.D | 44.500 |
hsync_sym/q2.Q | hsync_sym/XLXI_2/Q0.D | 44.500 |
hsync_sym/q3.Q | hsync_sym/XLXI_2/Q0.D | 44.500 |
hsync_sym/q6.Q | hsync_sym/XLXI_2/Q0.D | 44.500 |
hsync_sym/q7.Q | hsync_sym/XLXI_2/Q0.D | 44.500 |
hsync_sym/q1.Q | hsync_sym/q1.D | 37.000 |
hsync_sym/q1.Q | hsync_sym/q2.D | 37.000 |
hsync_sym/q1.Q | hsync_sym/q3.D | 37.000 |
hsync_sym/q1.Q | hsync_sym/q4.D | 37.000 |
hsync_sym/q1.Q | hsync_sym/q5.D | 37.000 |
hsync_sym/q1.Q | hsync_sym/q6.D | 37.000 |
hsync_sym/q1.Q | hsync_sym/q7.D | 37.000 |
hsync_sym/q2.Q | hsync_sym/q1.D | 37.000 |
hsync_sym/q2.Q | hsync_sym/q2.D | 37.000 |
hsync_sym/q2.Q | hsync_sym/q3.D | 37.000 |
hsync_sym/q2.Q | hsync_sym/q4.D | 37.000 |
hsync_sym/q2.Q | hsync_sym/q5.D | 37.000 |
hsync_sym/q2.Q | hsync_sym/q6.D | 37.000 |
hsync_sym/q2.Q | hsync_sym/q7.D | 37.000 |
hsync_sym/q3.Q | hsync_sym/q1.D | 37.000 |
hsync_sym/q3.Q | hsync_sym/q2.D | 37.000 |
hsync_sym/q3.Q | hsync_sym/q3.D | 37.000 |
hsync_sym/q3.Q | hsync_sym/q4.D | 37.000 |
hsync_sym/q3.Q | hsync_sym/q5.D | 37.000 |
hsync_sym/q3.Q | hsync_sym/q6.D | 37.000 |
hsync_sym/q3.Q | hsync_sym/q7.D | 37.000 |
hsync_sym/q6.Q | hsync_sym/q1.D | 37.000 |
hsync_sym/q6.Q | hsync_sym/q2.D | 37.000 |
hsync_sym/q6.Q | hsync_sym/q3.D | 37.000 |
hsync_sym/q6.Q | hsync_sym/q4.D | 37.000 |
hsync_sym/q6.Q | hsync_sym/q5.D | 37.000 |
hsync_sym/q6.Q | hsync_sym/q6.D | 37.000 |
hsync_sym/q6.Q | hsync_sym/q7.D | 37.000 |
hsync_sym/q7.Q | hsync_sym/q1.D | 37.000 |
hsync_sym/q7.Q | hsync_sym/q2.D | 37.000 |
hsync_sym/q7.Q | hsync_sym/q3.D | 37.000 |
hsync_sym/q7.Q | hsync_sym/q4.D | 37.000 |
hsync_sym/q7.Q | hsync_sym/q5.D | 37.000 |
hsync_sym/q7.Q | hsync_sym/q6.D | 37.000 |
hsync_sym/q7.Q | hsync_sym/q7.D | 37.000 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/q1.D | 26.500 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/q2.D | 26.500 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/q3.D | 26.500 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/q4.D | 26.500 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/q5.D | 26.500 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/q6.D | 26.500 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/q7.D | 26.500 |
hsync_sym/XLXI_2/Q0.Q | hsync_sym/XLXI_2/Q0.D | 19.000 |
hsync_sym/q4.Q | hsync_sym/q4.D | 19.000 |
hsync_sym/q4.Q | hsync_sym/q5.D | 19.000 |
hsync_sym/q4.Q | hsync_sym/q6.D | 19.000 |
hsync_sym/q4.Q | hsync_sym/q7.D | 19.000 |
hsync_sym/q5.Q | hsync_sym/q5.D | 19.000 |
hsync_sym/q5.Q | hsync_sym/q6.D | 19.000 |
hsync_sym/q5.Q | hsync_sym/q7.D | 19.000 |
m1_cycle_T3.Q | m1_cycle_T4.D | 19.000 |
Source | Destination | Delay |
---|---|---|
video_shifter/XLXN_77.Q | video_shifter/XLXN_79.D | 26.500 |
video_shifter/XLXN_81.Q | video_shifter/XLXN_83.D | 26.500 |
cpuclk.Q | cpuclk_inv.D | 19.000 |
video_shifter/XLXN_26.Q | video_shifter/XLXN_77.D | 19.000 |
video_shifter/XLXN_79.Q | video_shifter/XLXN_81.D | 19.000 |
video_shifter/XLXN_83.Q | video_shifter/XLXN_85.D | 19.000 |
video_shifter/XLXN_85.Q | video_shifter/XLXN_87.D | 19.000 |
video_shifter/XLXN_87.Q | black_on_white.D | 19.000 |
Source | Destination | Delay |
---|---|---|
a3.Q | a3.D | 19.000 |
a4.Q | a4.D | 19.000 |
a5.Q | a5.D | 19.000 |
a6.Q | a6.D | 19.000 |
a7.Q | a7.D | 19.000 |
a8.Q | a8.D | 19.000 |
forced_NOP_cycle.Q | forced_NOP_cycle.D | 19.000 |
invert.Q | invert.D | 19.000 |
Source | Destination | Delay |
---|---|---|
a0.Q | a1.D | 19.000 |
a0.Q | a2.D | 19.000 |
a1.Q | a2.D | 19.000 |
Source | Destination | Delay |
---|---|---|
a0.Q | a1.D | 19.000 |
a0.Q | a2.D | 19.000 |
a1.Q | a2.D | 19.000 |
Source | Destination | Delay |
---|---|---|
a0.Q | a1.D | 19.000 |
a0.Q | a2.D | 19.000 |
a1.Q | a2.D | 19.000 |
Source | Destination | Delay |
---|---|---|
a0.Q | a1.D | 19.000 |
a0.Q | a2.D | 19.000 |
a1.Q | a2.D | 19.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
Iorq | d1 | 39.500 |
Iorq | d2 | 39.500 |
Iorq | d3 | 39.500 |
Iorq | d4 | 39.500 |
Iorq | d6 | 39.500 |
Kbd1 | d1 | 39.500 |
Kbd2 | d2 | 39.500 |
Kbd3 | d3 | 39.500 |
Kbd4 | d4 | 39.500 |
Rd | d1 | 39.500 |
Rd | d2 | 39.500 |
Rd | d3 | 39.500 |
Rd | d4 | 39.500 |
Rd | d6 | 39.500 |
a0 | d1 | 39.500 |
a0 | d2 | 39.500 |
a0 | d3 | 39.500 |
a0 | d4 | 39.500 |
a0 | d6 | 39.500 |
usa_uk | d6 | 39.500 |
Iorq | d0 | 32.000 |
Iorq | d7 | 32.000 |
Kbd0 | d0 | 32.000 |
Rd | d0 | 32.000 |
Rd | d7 | 32.000 |
a0 | d0 | 32.000 |
a0 | d7 | 32.000 |
tape_in | d7 | 32.000 |
Invert_screen | luminance | 23.500 |
Mreq | Ramcs | 23.500 |
Mreq | Romcs | 23.500 |
Xin | Xout | 23.500 |
a14 | Ramcs | 23.500 |
a14 | Romcs | 23.500 |
zx80_zx81 | Nmi | 23.500 |