Sinclair ZX80 / ZX81 / Z88 Forums

Hi Luciano
the picture above is OK to generate /RAMCE:

download/file.php?id=4975

And to generate /OE you should use an AND gate: /RAMOE = /RS AND /RFSH (any of /RD or /RFSH LOW shall enable ram output and give a LOW at /RAMOE)

About capacitors: you should have approx. 100 nF next to each IC. Is that given?

Regards
Siggi

Thank you Siggi

I will try to test today.

I will check the capacitors.. i think there is 100nf on each IC.. but i will confirm

For RAMCS signal one question:

The ZX80 schematic uses A14´ and MREQ ,on nand gate inputs, to generate RAMCS... and the expansion uses A14 and MREQ ..

Using A14´ or A14 get the same results?

Regards

Luciano

Hi Siggi

I tested the logic suggested.. same results.

But i have some good news.. i changed the 62256 memory and added the eeprom 28c64 again

Now the image is very good.(attached)

Testing with the 27c64 , the problem returns ( or using the old 62256 and 27c64 or 28c64)

Maybe the EEPROM is faster?

I will try to investigate further..

Hi Luciano
I don't understand, that ROM (or something similar) affects the behaviour of RAM. Maybe there is a collision between ROM and RAM due to an error in address decoding the RAM or ROM area? Then not the speed of the ROM, but the strenght of its databus output drivers would more or less affect/destroy the RAM's output (at least during refresh cycles, where the HIRES pixels are read) .....
Maybe the ROM is always enabled while /RFSH is low??????

What is A14' (your previous posting)? The ZX81 does not have that signal (only the "real" A14). Grant's site seems to be "sleeping", so I cannot check his schema there ...

Regards
Siggi

Hi Siggi.

Yes, probably during low refresh period the ROM add some data on data bus.
I am planning to add some additional logic .. to disable the ROM or add some delay, during refresh period.
(just to understand better the problem)
Some idea about which signals needed to disable ROM in the right time? ( /RFSH only ?)

All the connections seems to be OK, because the clone works fine for all other programs.
(and now is working fine with 28c64 and new 62256

About A14´ is located at pin 9 on IC12 and IC13 pin 13 coming from IC6 pin 9
http://problemkaputt.de/zx80-sch.gif

Luciano wrote: ↑Thu Nov 23, 2017 7:44 pm Hi Siggi.

Yes, probably during low refresh period the ROM add some data on data bus.
I am planning to add some additional logic .. to disable the ROM or add some delay, during refresh period.
(just to understand better the problem)
Some idea about which signals needed to disable ROM in the right time? ( /RFSH only ?)

The ROM needs also to be enabled during RFSH! Otherwise you could not see the lowres character set, where the character generator patterns are stored in ROM!
The ROM should only be disabled by its address in memory: so the address decoder should enable the ROM in range 0-8K only by using MREQ and the address line A14 (or A14').

And the schema shows: the ROM is always enabled during refresh, because during refresh the multiplexer IC6 selects input 5, which is tied to GND and thus enables ROM! This problem could be solved, if you disconnet pin 5 grom GND an connect it to pin 6. The the ROM then will only be enabled by its address (MREQ and A14'), no more during ALL(!) refresh cycles.

But: I don't know, if that will result in other problems (I am not familiar with ZX80).

Regards
Siggi

Hi Siggi

Excellent Idea.. i will test today.

Actually is not a zx80 anymore .. because it has a NMI generator upgrade and the zx81 rom 8k.
http://searle.hostei.com/grant/zx80/zx80nmi.html

So , in "theory" is a zx81 .. that is why i am trying to solve this.. I want a 100% compatible clone. (if possible )

Thank you again

Regards

Luciano

Hi Luciano
one more hint: during REFRESH, the MREQ-signal is shorter than during normal READ/WRITE. Maybe that is the reason, why they used GND instead of MREQ (during refresh) to enable ROM (ROMCS is then active as long as REFRESH is low): they could use slow roms.

So if you want also to use slow (original) roms, you should connect A14 to pin 5 IC6: then the ROMCS during REFRESH will have the same length as before.

Regards
Siggi

Hi Siggi

Good News!!

Your idea worked very well. Perfect!

(Connecting pin 5 to A14 )

Even using the old 62256 sram,, 27c64 or 28c64 ,74LS or 74HC.. ALL combinations worked

I will do more tests.. but i think it solved the problem.. take a look at the pictures (from tv grabber) attached

Thanks a LOT !

Great news

Funny that I had studied that part of the ZX80 schematic a couple of months ago, I wondered why Sinclair had wired up that multiplexer input like that (pin 5). But I got distracted and never investigated any further...

Mark