Well now it's 90% working - just the XOR gate 74LVC1G386 missing but should be here monday or tuesday I think.
First I had problems with the timer NE556.
I changed to have the voltage of the hsync capacitor as reference for faster reaction when loosing sync instead of the vsync capacitor.
This has not been tested but thought this would be possible.
Well in fact I have the problem that during longer vsync the hsync pulse from the ZX81 is blocked and hsync comes from standby sync generator.
This could be solved easily through changing the components for hsync and vsync back.
So now the picture was stable even with standby sync active.
The next problem was the wrong timing of NE556 vsync, with about 15ms instead of 20ms.
I found some misterious swinging voltage when charging the capacitor for a period of several ms.
This could be solved with a power supply capacitor of 100uF at 5V power supply.
The NE556 is very sensitive for power supply ripple.
Didn't expect this. After all, it was running with the exact frequency and the swinging has gone.
I don't have a capacitor at the board, maybe could place a small one with about 4.7uF or so at power supply pins.
I have to check what capacitors are available not to big (0805 or 1206).
And I had problems with the 3.3V power delivered from the simple diode BAV199 for the LVL gates.
Had a significant ripple after vertical sync pulse, when drivers have to deliver current for the video output.
The LVL are very sensitive about power supply voltage ripple or noise.
Could stable this with a capacitor 100uF immediately with no ripple / swinging.
At the board I had place for a 100nF capacitor but has to be increased to a few uF I think.
I have to look for maybe same for the 5V.
For picture during LOAD I had to increase R11 from 22k to 39k.
Otherwise had some disturbing pulses at the output - not stable sync during LOAD.
With this change picture is perfect in normal mode and during LOAD.
I will add a video of it when finished with XOR gate.
Nice to see.
And I corrected the output resistors.
The driver output of the low voltage gates (LVL) are very good and impressive in comparison to general TTL logic.
Nearly no voltage loss at high output (when delivering about 10mA) and nearly no voltage loss when sourcing down to GND.
So high output is somewhere of 3.1V and low output is about 0.1V (with load !) with a power supply of 3.3V.
I changed R9 to 390R instead of 220R.
Output now is at 0.1V for sync level, 0.4V for black level and 1.1V for white level. Perfect.
Picture looks very good, very stable, very sharp.
I think better than my first circuit (ZX81CCP).
And power consumption is about 7mA with no load and about 16mA with 75R load at output.
Could increase max. 1mA with the missing XOR gate.
All changes are made now in the schematic.
Fortunately no changes for the board.

- ZX81SCP_sch.gif (20.84 KiB) Viewed 6967 times